At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. College education in Electronics Engineering or Computer Engineering Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. Functional simulation using Verilog/System Verilog. Good in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging. Checks and validation of package consistency. Familiarity with Power Flow (UPF/CPF). Able to collaborate with IP-development teams and facilitate high-quality releases. Maintaining package and release timelines for various projects. Time management skills enough to balance multiple high-priority projects. Bug reporting and resolution closure with IP providers Ability to debug synthesis/timing analysis constraints, reports, logs Ability to learn new tools/flows and develop methodology if needed. Ability to build and maintain close relationships with Designers and Application Engineers. Fastidious approach to building automated processes. Strong interpersonal and relationship-building skills. Additional Desirable Qualifications Familiarity with SerDes/DDR/other Design-IP’s & Analog design flows Familiarity with IP release and tracking management systems. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Introduction Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. Your Role And Responsibilities Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Preferred Education Master's Degree Required Technical And Professional Expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC.. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred Technical And Professional Experience Automation skills in PYTHON, PERL ,SKILL and/or TCL Show more Show less

Job Description M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Requirement M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Show more Show less

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Job Description At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Physical Design Engineer Experience: 4+ Years Job Specification Work with internal Design teams and Methodology teams to successfully Lead/implement Physical Designs of multiple blocks of Complex ASICs . The position requires good understanding of the physical design flow from RTL to GDS & several chips tapeout experience. The successful candidate should possess in-depth knowledge & experience in physical synthesis, design planning, floor planning, place & route, static timing analysis and design closure & physical verification Responsibilities Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation. Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc. Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow. Experienced in design automation. Understanding of Timing constraints, SI prevention, Power reduction. Must have prior experience with Synopsys/Cadence/Mentor place and route tools. Must have completed design in 16nm and or 7nm.. Proficient in Unix/TCL/Perl. Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability. Minimum Qualifications 4+ years experience in ASIC physical design Experience with block implementation, extraction, timing and or full-chip designs Strong communication skills Strong hands-on TCL/Perl development skills Preferred Qualifications Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project Track record of taping out complex chips on advanced process nodes About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need. Show more Show less

Principal STA / Synthesis Engineer Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Engineers for the following roles. Constraint development Constraint management Constraint validation Chip top level synthesis, sta and Timing Closure. RTL2GDS flow. Ability to handle synthesis,sta, lec, upf flow methodologies. TCL/perl/python scripting. Candidate with 12-17 yrs exp in Synthesis / STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Design Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Hands-on experience in LEC along with strong debugging skills for resolving issues/aborts. Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at block/top level using tools like DMSA Excellent debugging skills in timing convergence issues and ability to come up with creative solutions . Technical leadership and ability to mentor and make the team deliver. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Job Description Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background Masters, Bachelors: Electrical Engineering , VLSI , Embedded and VLSI , ECE Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3063801 Show more Show less

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute The SVT/PV Engineer will develop test strategies, automation script development, and execute test plans for Ciena’s Packet Optical products, focusing on OTN Transport, Switching and NMS. Key Responsibilities Develop and automate test strategies for Telecom networks. Create and execute test plans using TCL/Python. Identify and automate test scenarios. Debug and resolve defects with design teams. Ensure compliance with industry standards (ITU-T, IETF, IEEE, ANSI). Must Have OTN Transport & Switching Test Automation (TCL/Python) Defect Analysis & Debugging Telecom Network Testing Bachelor’s/Master’s in Electronics, Computer Science, or Optical Communications. 2+ years in Telecom System Testing. Experience in test planning, automation, and debugging. Impact Metrics Improved test efficiency & automation coverage Reduction in defect leakage & debugging time Compliance with test quality standards Nice-to-Have Skills Exposure to different NBIs – REST, NETCONF, gRPC and Photonics/DWDM Familiarity with Test Equipment & Performance Benchmarking. Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Show more Show less

Company Qualcomm India Private Limited Job Area Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background Masters, Bachelors: Electrical Engineering , VLSI , Embedded and VLSI , ECE Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3063801 Show more Show less

To work as a timing engineer (STA) and taking care of end to end timing responsibilities for complex SoC projects. Job Description In your new role you will: Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT’s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Your Profile You are best equipped for this task if you have: Bachelors or Masters in Electrical/Electronics Engineering. BE/B.Tech/M.Tech with 6+ years. Project leading knowledge is preferred. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidate should have strong STA fundamentals. Has done timing sign-off including timing margin calculations. independently, hands-on STA lead of projects. Experience in handling STA of multi-power domain designs & constraint mode merging. STA flow development, abstraction with bottleneck identification. Proficient in design margins and SDC constructs. TAT reduction in multi-mode, multi power domain/designs. Generate timing ECOs for Physical design. Drive ambitious schedules and enables dependent teams to accomplish. Interface to design team and PD team and drive TAT reduction for PD. Has experience in mentoring junior engineers. Proficient with EDA tools from Synopsys/Cadence. Excellent analytical & communication skills. Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone. Proficient in Tcl and Perl or other scripting relevant language is a plus. Contact: Swati.Gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

ACL Digital is looking for a talented and experienced STA (Static Timing Analysis) Engineer to join our growing VLSI team! If you have experience in timing analysis and have worked on full-chip designs , we want to hear from you. Role & Responsibilities: Drive full-chip STA from RTL to GDSII Develop and validate timing constraints (SDC) for complex SoCs Perform timing closure and sign-off using tools like PrimeTime Collaborate with RTL, physical design, and DFT teams for ECOs and timing fixes Analyze timing reports, debug violations, and propose optimization strategies Key Requirements: 5–10 years of hands-on experience in Static Timing Analysis Proven track record in full-chip STA and timing sign-off Strong knowledge of timing constraints, multi-mode/multi-corner (MMMC) flows Familiar with scripting (TCL, Perl) and STA tools (Synopsys PrimeTime preferred) Excellent analytical, debugging, and cross-team communication skills Location: Pune/Bangalore Notice period: Immediate Why ACL Digital? At ACL Digital, you’ll be part of a fast-paced team delivering next-gen semiconductor solutions. We offer opportunities to work on cutting-edge technology with top-tier clients across the globe. Show more Show less

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Responsible for developing & testing of software Responsible for generating documents, such as Requirements Spec, design, user-guide, API spec, etc., Skills Must have Candidate should have 7+ yrs experience Experience: § Experience in designing complex multithreaded Performant SW § Experience in designing SW API interfaces. § Experience in C/C++ programming § Experience with Multi-threaded software development in Linux environment § Experience with Embedded IP subsystems e.g. Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA § Experience with development of software targeted for x86, standalone and RTOS platforms § Experience in low level driver development, register interface programming, general algorithms and data structures, bootloaders/Uboot § Experience working with and integrating open-source software § Strong debugging skills at device and board level using JTAG debuggers § Experience in Software programming for FPGAs is an advantage § Scripting language experience like Perl, Python or TCL Nice to have § Excellent interpersonal, written and verbal communication skills § Excellent communication, problem solving and analytical skills § Education: B.tech/M.Tech in CSE/IT/ECE/EEE/E&I Other Languages English: B2 Upper Intermediate Seniority Senior Hyderabad, IN, India Req. VR-114911 C/C++ Automotive Industry 06/06/2025 Req. VR-114911

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Software Engineer (Development and test) Responsible for developing & testing of software Responsible for generating documents, such as design, user-guide, test plan, test spec, test report etc., Skills Must have Candidate should have 5+ yrs experience Experience: § Experience in C/C++ programming § Experience with Multi-threaded software development in Linux environment § Experience with Embedded IP subsystems e.g. Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA § Experience with development of software targeted for x86, standalone and RTOS platforms § Experience in low level driver development, register interface programming, general algorithms and data structures, bootloaders/Uboot § Experience with CI tools, test automation, etc. § Strong debugging skills at device and board level using JTAG debuggers § Experience in Software programming for FPGAs is an advantage § Scripting language experience like Perl, Python or TCL Nice to have § Excellent interpersonal, written and verbal communication skills § Excellent communication, problem solving and analytical skills § Education: B.tech/M.Tech in CSE/IT/ECE/EEE/E&I Other Languages English: B2 Upper Intermediate Seniority Regular Hyderabad, IN, India Req. VR-114913 C/C++ Automotive Industry 06/06/2025 Req. VR-114913

Role: Physical Design Engineer Experience Required: 5-15 Years Work location: Noida Minimum Experience required is 5 Years in Physical Design Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry. Sound expertise in Tcl, Perl, and Shell scripting. Technically sound & good team player Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence Innovus / Encounter) is a must. Experience with latest technology (28nm,16nm,7 nm) Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification experience is a Plus. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12-15 years of experience with a Bachelor's/ Master’s degree in Electrical/ Electronics engineering Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071550 Show more Show less

Staff GPU Verification Engineer Bangalore India, Hyderabad India Experienced Professional Posted 4 Jun 2025 502669 The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or connectivity processor and related IP. You will: Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off Create verification plans, develop and maintain UVM testbench components Track and report verification metrics and closure Participate in all stages of design specification definition providing feedback from the verification perspective Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans. Be responsible for the definition, effort estimation and tracking of your own work Be able to influence and advance our GPU verification methodology Have the opportunity to lead, coach and mentor other members of the team Participate in design and verification reviews and recommend improvements About you Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Have a proven track record of developing verification environments for complex RTL designs Have excellent understanding of constrained-random verification methodology and challenges of verification closure Be confident in defining verification requirements, and work out the implementation approach and details of a testbench Be able to do root-cause analysis of complex issues and resolve them in a timely manner Have excellent knowledge of SystemVerilog and UVM Be able to develop new verification flows Have working knowledge of ASIC design methodologies, flows and tools Be able to plan, estimate and track your own work Experience working on multiple projects at one time The skill to be able to communicate technical issues both in written form and verbally You might also have: Experience leading teams Graphics/GPU/CPU/SoC knowledge Experience in wider verification technologies, such formal property based verification and code mutation Skill scripting in Python, TCL, Perl, SystemC, C++ experience Understanding of functional safety standards such as ISO26262 Who we are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets. Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership. Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces. We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before. So come join us if you're wanting that something more Bring your talent, curiosity and expertise and we’ll help you do the rest. You’ll be part of one of the world’s most exciting companies who are one of the leaders in semiconductor IP solutions. As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology. Additional information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec.com.

Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. EDA Infrastructure Engineers are individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, EDA Infrastructure Responsibilities: Front End implementation flow development and support Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation Manage the internal EDA license requests, installation and license forecast as well as EDA tool installation and maintenance Work with internal infrastructure team on compute grid, storage management and job scheduling architecture, efficiency and maintenance Work with internal infrastructure team on adapting Meta infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management and reporting RTL2GDS flow development and support Physical Design implementation flow development and support Minimum Qualifications: Knowledge of front-end and back-end ASIC tools and flows Experience with RTL design using SystemVerilog or other HDL 8+ years of experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments Experience with ASIC EDA infrastructure (compute, storage, job scheduling) management, maintenance and support Experience with developing and supporting solutions for ASIC design environment and infrastructure Experience with communicating across functional internal teams and with vendors Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Experience setting up EDA infrastructure from scratch User experience and customer oriented solutions About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Role Familiar with Physical Design Life cycle of chip development, especially Floorplanning and PnR Hands on PD execution at block/SoC level along with PPA improvements Strong understanding of the technology and PD Flow Methodology enablement. Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them Provide tool support and issue debugging services to physical design team engineers across various sites Develop and maintain 3rd party tool integration and productivity enhancement routines Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set Strong programming experience & Proficiency in Python/Tcl/C++ Understand physical design flows using Innovus/fc/icc2 tools Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory Basic understanding of Timing/Formal verification/Physical verification/extraction are desired Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory* Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069347 Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 12+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071473 Show more Show less

Job Description And Requirements Design, development, troubleshooting, and debugging of multi-Gb/s SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team. Requirements. Looking for 1-2 years of experience in Analog design with master's degree or 2-4 years of experience in in Analog design with bachelor's degree. In depth familiarity with transistor level circuit design - sound CMOS design fundamentals Exposure to SERDES sub circuits (ie. TX, RX ,adaptive Equalizers-(FIR, DFE, CTLE), PLL, DLL, BGR, Regulators, ADC etc) Aware of ESD issues (ie. circuit techniques, layout) Familiarity with custom digital design (ie. high speed logic paths) Knowledge of design for reliability (ie. EM, IR, aging, etc…) Knowledge of layout effects (ie. matching, reliability, proximity effects, etc…) Familiar with Custom design and/or Cadence, HSPICE, HSIM,Ultrasim,etc Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB etc…) Some knowledge of system level budgeting (ie. jitter, amplitude, noise, etc…) Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise Good communication and documentation skills. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a Digital Verification Senior Engineer, you are passionate about technology and eager to drive pre-silicon functional verification of High-Speed PHY IPs. You have a dynamic personality and a strong desire to learn and excel in pre-silicon verification activities. With a solid understanding of digital design and HDL implementation, you are ready to take on complex challenges and contribute significantly to our innovative projects. You thrive in a diverse team environment and possess excellent debug and diagnostic skills, along with proficiency in scripting and automation using TCL, PERL, or Python. What You’ll Be Doing: Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You’ll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python. Who You Are: You are a detail-oriented, analytical thinker with a strong problem-solving mindset. You possess excellent communication and collaboration skills, enabling you to work effectively within a diverse team. Your passion for technology drives you to stay updated with the latest advancements and continuously improve your skills. You are proactive, adaptable, and committed to delivering high-quality results in a fast-paced environment. The Team You’ll Be A Part Of: You will join a dedicated team of engineers focused on the verification of High-Speed PHY IPs. Our team is committed to innovation and excellence, working collaboratively to ensure the highest standards of quality and performance. We value diversity and inclusivity, fostering an environment where every team member can thrive and contribute to our collective success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly. What You’ll Be Doing: Supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality. Applying extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption. Interacting with other Synopsys R&D members and customers to understand their needs and product goals. Contributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules. Exercising judgment in developing methods, techniques, and evaluation criteria to meet project goals. Collaborating with a team of enthusiastic and creative engineers to drive innovation and excellence. The Impact You Will Have: Enhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption. Driving continuous improvement in software development processes and practices. Contributing to the development of cutting-edge technologies that power innovations in various industries. Helping Synopsys maintain its leadership position in the market by delivering high-performance solutions. Influencing the direction and success of our hardware verification tools through your expertise and innovation. Fostering a collaborative and innovative work environment that encourages growth and learning. What You’ll Need: A Bachelor’s degree in Electrical/Electronics/Computer-Science Engineering with a minimum of 8 years of related experience, or a Master’s degree with 6 years of relevant experience. In-depth understanding of data structures, algorithms, and their applications. Excellent software development experience with C/C++ on UNIX/Linux platforms. Exposure to Python, TCL, and shell scripting languages is preferable. Exposure to HDL languages like Verilog or System Verilog is desirable, with a willingness to learn their nuances. Demonstrated history of good analytical, debugging, and problem-solving skills. Experience with complex and large software code-based tool development. Who You Are: You are a motivated and enthusiastic engineer who excels in both independent and collaborative settings. You have a solid desire to learn and explore new technologies, and you exercise good judgment in developing methods and techniques to meet project goals. Your excellent written and oral communication skills in English enable you to collaborate effectively and present your ideas clearly. Special consideration will be given to candidates with a background in hardware functional verification and/or synthesis techniques, as well as knowledge of software specification, design processes, and regression testing. The Team You’ll Be A Part Of: You will join the Hardware Assisted Verification team at Synopsys, a group of dedicated and innovative engineers focused on developing and enhancing our verification tools. Our team is committed to pushing the boundaries of technology and delivering high-performance solutions that meet the needs of our customers. We work in a collaborative and dynamic environment, where creativity and innovation are encouraged and valued. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Job Requirements 3 to 6 years of exp in Hands on Chip top and Block level Timing closure. Netlist and constraint sign in checks and validation. Timing constraint development at Full chip level and clean up. Multimode multi corner timing knowledge and timing closure at Top and Block level. Top level timing closure with sing off STA. Top level ECO implementation strategy development for netlist, RTL and timing level changes. Scripting experience in Perl/TCL Excellent debugging skills and ability to come up with creative solutions. Technologies from 28nm and below. Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. IO Planning and bump planning Having proficiency with either PrimeTime, Tempus and Innovus is must Work Experience Netlist and constraint sign in checks and validation. Timing constraint development at Full chip level and clean up. Performing floor-planning and routing studies and implementation at block and full-chip level Show more Show less

Job Requirements The responsibilities will include several of the following, but not be limited to: Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. IO Planning and bump planning Closely working with Package team and reaching Die file milestones Full chip and partition level timing analysis. Evaluate low power techniques and power reduction opportunities Perform clock distribution design and analysis Perform Physical verification activities at full-chip level. Drive technical activities of physical design during technology readiness, design & execution In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes Work Experience Experience Range:- 4Yrs - 10 Yrs Should be able to handle PD task independently and also should be able to manage the small team Should have experience in handling >1M instance count, 1 GHz frequency designs Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Show more Show less