1570 Tcl Jobs - Page 9

Job Role: 3DEXPERIENCE Developer Job Location: Bangalore Work Mode: (Hybrid) Experience 3-6+ years Job Summary: We are seeking skilled 3DEXPERIENCE Developers with 36 years of experience to join our engineering team. The ideal candidates will have hands-on experience in ENOVIA customization and be proficient in MQL, TCL, EKL, and CAA. You will work closely with cross-functional teams to develop, customize, and enhance 3DEXPERIENCE applications based on business needs. Key Responsibilities: Develop and customize 3DEXPERIENCE/ENOVIA applications using MQL (Matrix Query Language), TCL (Tool Command Language), EKL (Engineering Knowledge Language), and CAA (Component Application Architecture). Implement business logic using EKL in 3DEXPERIENCE dashboards and widgets. Customize and extend out-of-the-box (OOTB) ENOVIA apps. Develop integrations with external systems (e.g., ERP, CAD tools). Perform bug fixing, performance tuning, and upgrades for ENOVIA components. Analyze requirements and translate them into technical designs. Provide technical documentation and support user acceptance testing (UAT). Collaborate with functional teams and provide post-deployment support. Key Skills and Tools: Languages & Scripting: MQL, TCL, EKL Platform Expertise: ENOVIA 3DEXPERIENCE (2019x and above preferred) Development Framework: CAA (Component Application Architecture) Other Skills: Java, JavaScript (optional but a plus), 3DEXPERIENCE data model understanding Strong debugging and problem-solving abilities Knowledge of data migration and upgrade processes in ENOVIA (added advantage) Preferred Qualifications: Bachelors or masters degree in computer science, Mechanical Engineering, or related field Dassault Systems certification (optional but preferred) Experience working in Agile/Scrum environments

Job Description Key Responsibilities – AMS Verification Work in Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Hands-on experience with AMS simulation environments using Cadence, Synopsys, or Mentor tools. Solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Strong knowledge of Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling. Experience in block-level and chip-level AMS verification, including top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective is a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation. Fluency with Cadence Virtuoso-based analog design flow, including schematic capture, simulator/netlist configuration, and SPICE simulation. Ability to extract, analyze, and document simulation results and present findings in technical reviews. Familiarity with test plan development, AMS modeling, and verification methodologies. Supporting post-silicon validation and correlating measurement data with simulations. Team-oriented, proactive, and able to contribute in a multi-site development environment.

To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. • Leading a project for AMS requirements is a value add. • Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools • Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. • Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) • Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus • Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected • Experience working on AMS Verification on multiple SOC’s or sub-systems • Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus • Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment • Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations • Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. • Develop and execute top-level test cases, self-checking test benches and regressions suites • Developing and validating high-performance behavior models • Verifying of block-level and chip-level functionality and performance • Team player with good communication skills and previous experience in delivering solutions for a multi-national client • Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience • Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. • Ability to extract simulation results, capture in a document and present to the team for peer review • Supporting silicon evaluation and comparing measurement results with simulations • UVM and assertion knowledge would be an advantage

To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. • Leading a project for AMS requirements is a value add. • Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools • Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. • Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) • Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus • Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected • Experience working on AMS Verification on multiple SOC’s or sub-systems • Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus • Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment • Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations • Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. • Develop and execute top-level test cases, self-checking test benches and regressions suites • Developing and validating high-performance behavior models • Verifying of block-level and chip-level functionality and performance • Team player with good communication skills and previous experience in delivering solutions for a multi-national client • Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience • Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. • Ability to extract simulation results, capture in a document and present to the team for peer review • Supporting silicon evaluation and comparing measurement results with simulations • UVM and assertion knowledge would be an advantage

Job Requirements Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills. Work Experience Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills.

Alternate Job Titles: Applications Engineering, Sr Engineer Technical Support Engineer – Senior Level We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineering professional, eager to make a tangible impact in the semiconductor industry. With a strong foundation in electronics, computer engineering, or a related discipline, you thrive in dynamic, fast-paced environments where learning never stops. You enjoy solving complex technical challenges, collaborating with diverse teams, and engaging directly with customers to deliver innovative solutions. Your ability to communicate technical concepts to both technical and non-technical stakeholders sets you apart. You are proactive, resourceful, and committed to continuous self-improvement. Your adaptability and curiosity drive you to stay ahead of technology trends, and you take pride in mentoring peers as well as learning from them. You value inclusivity, respect different viewpoints, and believe that the best results come from teamwork. You are excited to work on projects that have real-world impact and are motivated by the opportunity to influence how cutting-edge technology shapes the future. If you’re looking to grow your career alongside some of the brightest minds in the industry and contribute to game-changing advancements, Synopsys is the place for you. What You’ll Be Doing: Collaborating with customers to understand their technical requirements and provide tailored solutions using Synopsys products. Delivering technical support and troubleshooting for complex issues throughout the product lifecycle, ensuring customer satisfaction. Conducting product demonstrations, training sessions, and workshops to empower users and promote product adoption. Working closely with R&D and product management teams to relay customer feedback and influence product roadmap decisions. Developing technical collateral including application notes, best practices, and white papers to facilitate customer success. Participating in pre-sales activities, including technical presentations and proof-of-concept evaluations. Staying abreast of industry trends and emerging technologies to provide strategic guidance to customers and internal teams. The Impact You Will Have: Accelerate customer success by ensuring seamless integration and optimal use of Synopsys solutions in their workflows. Bridge the gap between customer needs and product capabilities, driving continuous improvement and innovation. Enhance customer satisfaction through timely and effective technical support, fostering long-term partnerships. Influence product development by providing actionable feedback from real-world customer engagements. Expand Synopsys’ market reach by enabling customers to maximize the value of our technology. Contribute to a collaborative, knowledge-sharing culture that elevates the performance of the entire team. What You’ll Need: Bachelor’s or Master’s degree in Electronics, Computer Engineering, or a related technical field. 5+ years of experience in application engineering, technical support, or a relevant engineering role. Strong understanding of semiconductor design flows, EDA tools, and/or IP integration methodologies. Hands-on experience with scripting languages (e.g., Python, TCL, Perl) and familiarity with Linux/Unix environments. Proven ability to analyze and resolve complex technical issues in a timely manner. Excellent written and verbal communication skills for technical documentation and customer interaction. Who You Are: Proactive problem solver with a customer-first mindset. Strong collaborator who enjoys working in diverse, cross-functional teams. Adaptable and resilient in the face of shifting priorities and technical challenges. Excellent communicator with the ability to explain complex concepts clearly. Continuous learner, open to feedback, and eager to grow professionally. Detail-oriented and organized, with strong time management skills.

Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and apply your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect In this role based in Hyderabad - India, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What We're Looking For Completed a Bachelor’s Degree in Electronics/Electrical Engineering or related fields and have 4-8 years of related professional experience OR a Master’s degree and/or PhD in Electronics/Electrical Engineering or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis. Good understanding of standard Synthesis to GDS flows and methodology. Good scripting skills in languages such as Perl, tcl, and Python. Good understanding of digital logic and computer architecture. Hands-on experience in advanced technology nodes upto 2nm. Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC. Strong experience in block level signoff power, timing, PV closure & debugging skills. Good top level and full-chip experience is an added advantage Knowledge of Verilog/VHDL. Good communication skills and self-discipline contributing in a team environment. Ability to independently drive subsystems/IPs P&R and signoff closure working with global teams. Ability to mentor juniors and be involved in team development activities. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

We’re building an Agentic AI Platform that lets enterprises solve real business problems using Agentic AI workflows. From utility operations to legal document review; our mission is to let AI agents think, act, and deliver; fast, secure and locally. We’re looking for an Agentic AI Engineer who’s hungry to learn and ship. If you’re ready to build with cutting-edge frameworks like Lang Chain, CrewAI, Lang Graph, Google ADK and more and can translate real enterprise problems into intelligent multi-agent workflows, this role is for you. What You’ll Do Build and deploy AI agents using open-source agentic frameworks Explore and integrate models from OpenAI, Mistral, Gemini, Llama, Claude, etc. Use tools like Retrieval-Augmented Generation (RAG), knowledge graphs, and vector stores Work with product managers and domain experts to solve real problems (not just prototypes) Continuously test and refine agent behavior across different enterprise domains (utilities, legal, marketing, supply chain) Actively contribute to evolving our proprietary DataInsightAI platform Must-Have Skills At least 1+ years of hands-on experience implementing a enterprise level Gen AI project that has gone live. Strong Python skills (Async, FastAPI, LangChain/CrewAI or similar) Experience working with LLMs (OpenAI, Llama, Claude, Gemini, etc.) Familiar with agentic AI workflows, prompt chaining, and tool use Understanding of RAG, vector databases (like FAISS, Qdrant, Weaviate) Curiosity-driven mindset, fast learner, hands-on coder Ability to simplify complex problems and build MVPs fast Nice to Have Worked on multi-agent architectures or fine-tuned LLMs Used graph databases (Neo4j) or custom knowledge stores Experience deploying on Azure/AWS/GCP Familiarity with LangGraph or Google ADK Why Join Us? Work on cutting-edge agentic AI every day Be part of a lean team with real ownership Ship fast and solve real enterprise challenges Backed by InTimeTec, with a strong AI/ML engineering culture

About IDP IDP is the global leader in international education services, delivering global success to students, test takers and our partners, through trusted human relationships, digital technology and customer research. An Australian-listed company, we operate in more than 50 countries around the world. Our team is comprised of over 7,000 people of various nationalities, ages and cultural backgrounds. Proudly customer-first, our expert people are powered by global technology. Together, we offer unmatched services, helping local dreams become realities, all over the world. Learn more at www.careers.idp.com Role purpose We are seeking a highly skilled and experienced engineering manager to join our team. In this role, you will be responsible for leading and coordinating multiple projects across diverse teams. Your primary focus will be on developing efficient processes, executing effective strategies, and ensuring the timely completion of projects. As an engineering manager, you will play a key role in researching and developing innovative products. You will also be responsible for creating project budgets and overseeing their successful execution throughout the year. Collaborating closely with various teams, you will ensure that projects are delivered on schedule and within budget, maintaining a high level of quality and adherence to organizational objectives. Key accountabilities Delight our customers by delivering prompt, professional, and thorough solutions to their IT needs consistent with the demands of our growing business. Taking an end-to-end approach to service management and following through on service delivery through technology and other related resolver teams. Monitoring the current integrated Contact Center solution via integration, application, and network dashboards. Interrogating and understanding data produced from the monitoring dashboard tools. Continual Service Improvements and recommendations based on lessons learnt through incident and problem management and system monitoring. Service now: Triage Incident Management on level 2 support, troubleshoot problem management using the ITIL framework. Work in 24/7 rotational shift and ensure incidents are triaged and resolved within the agreed SLA Support the Contact Centre System Administrator for product enhancements, implementations, unit testing, and coordination of changes to the Contact Centre cloud platforms, as required for system configuration on ACD and IVR routing rules, menus, users, agent skills, supervisors, hours of operations, teams, points of contact, dialing lists and rules, queues and other messaging, call recording services, studio scripting, and other components. Collaborate with the System Administrator, developers, and cross-functional teams across IDP’s integrated landscape Support in creating new and maintaining existing technical documentation. Liaison with third-party vendors, partners, and suppliers, including Verizon, Nice inContact, TCL, Airtel, and Genesys. Creating of monthly service level performance reports and any other reports required Relationships Internal Global Student Placement & IELTS Contact Centre teams Service Desk team System Administrator DigiTech team Student Placement Operations team Student placement Marketing team Student placement Tech & Development teams External Third-party vendors, partners and suppliers, including Verizon, Nice InContact, Connect, TCL and Airtel Required Experience Essential Requirements Bachelor’s degree or relevant professional engineering qualification with major in information technology computer science, information science, computer systems analysis, or a related field. 5 to 6 years of professional experience with minimum 3 to 4 years of experience in contact centre tech support or telephony technology. Willing to work in 24/7 rotational shift Knowledge and experience in effectively working with the ITIL framework Ability to effectively articulate technical challenges and solutions Experience in supporting customers around the globe and willing to work in shift hours Personal profile: analytical, inquisitive, service and team-oriented, friendly demeanour adopter. Desirable Requirements Previous mandatory Genesys PureCloud and optional Nice inContact experience Mandatory: Experience with complex data and/or voice networks, ISDN PRI, SIP and hosted PBX Experience in handling GSM, SBC, Edge, Network routers and voice Gateways Experience with network and application monitoring tools especially Splunk. Exposure to SAP Cloud products namely C4C and Marketo, AWS, middleware support or any CRM application Mandatory: Contact Centre network, ACD/IVR, dialler, workforce management, software or other solution operations or technical experience like Avaya Cisco etc...

Category Application Development and Support Location Hyderabad, Telangana Job family Software Engineering Shift Evening Employee type Regular Full-Time Overall 3-5 years working in IT, as Middleware IT professional working with Infor’s Cloverleaf Suite (Cloverleaf Interface Engine, Secure Courier, Global Monitor, Secure Web Services) Cloverleaf Level 2 certification or comparable experience required. Minimum 3 years of TCL programming Design, develop, and unit test Infor’s Cloverleaf Suite of applications using agile and waterfall methodologies. Troubleshoot and debug services using the Cloverleaf’s tools and logs provided with the Cloverleaf Suite of products. Strong understanding and experience in various versions of HL7 v2.x, v3, XML and JSON structures. Should have experience in end-to-end monitoring of message tclproc’s and xlates. Understanding of Firewalls to request firewall rules. Knowledge of F5 load balancers and DNS networking is required. Should have some experience with tcp/ip sockets and ports, FTP, sFTP, and HL7 MLLP. Should have experience of working in Healthcare Industry (or similar) to understand the data security requirements like PCI/HIPPA/SOX/PHI etc. Web Service programming using TCL and Cloverleaf to handle SOAP and RestFul interfaces Good understanding of the FHIR standard Working knowledge of the Infor Cloverleaf FHIR server and service a plus View more

Category Engineering Hire Type Employee Job ID 12302 Remote Eligible No Date Posted 20/07/2025 Alternate Job Titles: Applications Engineering, Sr Engineer Technical Support Engineer – Senior Level We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineering professional, eager to make a tangible impact in the semiconductor industry. With a strong foundation in electronics, computer engineering, or a related discipline, you thrive in dynamic, fast-paced environments where learning never stops. You enjoy solving complex technical challenges, collaborating with diverse teams, and engaging directly with customers to deliver innovative solutions. Your ability to communicate technical concepts to both technical and non-technical stakeholders sets you apart. You are proactive, resourceful, and committed to continuous self-improvement. Your adaptability and curiosity drive you to stay ahead of technology trends, and you take pride in mentoring peers as well as learning from them. You value inclusivity, respect different viewpoints, and believe that the best results come from teamwork. You are excited to work on projects that have real-world impact and are motivated by the opportunity to influence how cutting-edge technology shapes the future. If you’re looking to grow your career alongside some of the brightest minds in the industry and contribute to game-changing advancements, Synopsys is the place for you. What You’ll Be Doing: Collaborating with customers to understand their technical requirements and provide tailored solutions using Synopsys products. Delivering technical support and troubleshooting for complex issues throughout the product lifecycle, ensuring customer satisfaction. Conducting product demonstrations, training sessions, and workshops to empower users and promote product adoption. Working closely with R&D and product management teams to relay customer feedback and influence product roadmap decisions. Developing technical collateral including application notes, best practices, and white papers to facilitate customer success. Participating in pre-sales activities, including technical presentations and proof-of-concept evaluations. Staying abreast of industry trends and emerging technologies to provide strategic guidance to customers and internal teams. The Impact You Will Have: Accelerate customer success by ensuring seamless integration and optimal use of Synopsys solutions in their workflows. Bridge the gap between customer needs and product capabilities, driving continuous improvement and innovation. Enhance customer satisfaction through timely and effective technical support, fostering long-term partnerships. Influence product development by providing actionable feedback from real-world customer engagements. Expand Synopsys’ market reach by enabling customers to maximize the value of our technology. Contribute to a collaborative, knowledge-sharing culture that elevates the performance of the entire team. What You’ll Need: Bachelor’s or Master’s degree in Electronics, Computer Engineering, or a related technical field. 5+ years of experience in application engineering, technical support, or a relevant engineering role. Strong understanding of semiconductor design flows, EDA tools, and/or IP integration methodologies. Hands-on experience with scripting languages (e.g., Python, TCL, Perl) and familiarity with Linux/Unix environments. Proven ability to analyze and resolve complex technical issues in a timely manner. Excellent written and verbal communication skills for technical documentation and customer interaction. Who You Are: Proactive problem solver with a customer-first mindset. Strong collaborator who enjoys working in diverse, cross-functional teams. Adaptable and resilient in the face of shifting priorities and technical challenges. Excellent communicator with the ability to explain complex concepts clearly. Continuous learner, open to feedback, and eager to grow professionally. Detail-oriented and organized, with strong time management skills. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 12162 Remote Eligible No Date Posted 20/07/2025 Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

STA setup, convergence, reviews, and signoff for scan Review of Unconstrained endpoints and check timing reports Working proficiency with tcl, python scripting Previous experience with ADI flows for STA preferred

3-15 years of experience in CATIA/CATScript/EKLAddition on Excel VBA knowledge SharePoint and Microsoft toolsAbility to work on tight deadlines and a team player. Required Candidate profile Excellent knowledge of Design Customization Excellent knowledge on Scripting and rule customizations

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - SENIOR SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS Work with multi-functional teams and handling schedules The successful candidate may also be responsible of: Debugging and verifying block-/chip-level DFT/DFX features Porting or creating the DFT/DFX verification environment Block/Chip test plan creation and development Stimulus writing and debug, and regression clean-up Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques Stimulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Provide technical support to other teams Preferred Experience Minimum 5 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Strong problem-solving skills. Team player with strong communication skills. Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in scripting languages like TCL and Perl. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 2+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in the aforementioned fields is also acceptable. Applicants with 1-5 years of experience are encouraged to apply. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm at disability-accommodations@qualcomm.com or refer to their toll-free number for assistance. Qualcomm also emphasizes the importance of compliance with company policies and procedures, including security measures for protecting confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities directly with Qualcomm. Agency submissions will be considered unsolicited, and Qualcomm does not accept unsolicited resumes or applications from agencies. For further details about this role, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to enabling next-generation experiences and driving digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems across a wide range of areas such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. Collaborating with cross-functional teams, Qualcomm Hardware Engineers play a crucial role in developing cutting-edge products that meet performance requirements. To be considered for this role, you should possess a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field, along with relevant work experience. We are currently looking for an EM/IR Methodology Engineer to join our team. This role focuses on developing and maintaining methodologies for Electromigration (EM) and Voltage Drop (IR) analysis to ensure robust and reliable designs in advanced semiconductor technologies. The ideal candidate will work closely with various teams to optimize power delivery networks and ensure compliance with EM/IR standards. Key Responsibilities: - Developing, validating, and optimizing methodologies for EM and IR analysis in advanced semiconductor designs. - Collaborating with design, CAD, and physical implementation teams to optimize power delivery networks. - Enhancing and automating workflows to improve PDN analysis efficiency. - Partnering with EDA tool vendors to enhance and customize EM/IR analysis tools. - Supporting design teams in EM/IR verification and sign-off. Required Skills and Qualifications: - Bachelors or Masters degree in Electronics, Electrical Engineering, or a related field. - 3-7 years of experience in EM/IR analysis or physical design methodology. - Strong understanding of EM and IR concepts and their impact on circuit reliability. - Hands-on experience with EM/IR analysis tools such as Voltus, RedHawk, Totem, or equivalent. - Experience with 2.5D/3D-IC, CoWoS, InFO, and WoW technologies. - Exposure to AI/ML concepts will be a bonus. - Proficiency in scripting languages such as Python, Perl, or Tcl for workflow automation. - Good understanding of STA concepts. - Strong problem-solving and analytical skills. - Excellent communication and teamwork skills. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For accommodation requests during the application/hiring process, please contact Qualcomm. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs directly at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. You will collaborate with cross-functional teams to ensure that the solutions meet performance requirements and contribute to the overall success of the projects. The ideal candidate for this role should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of experience in Hardware Engineering. Alternatively, a Master's degree with 5+ years or a PhD with 4+ years of relevant work experience will also be considered. It is essential to have expertise in physical design, especially in DDRPhy /PCIE-high speed interface PD or 3DIC, and timing signoff experience with SNPS/CDNS tools. Proficiency in automation skills like python, Perl, or TCL is required to drive improvements in Power, Performance, and Area (PPA). The successful candidate should have a strong background in PDN, IR signoff, Physical verification knowledge, RDL-design, Bump Spec understanding, and experience working on multiple technology nodes in advanced processes. Familiarity with low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating is also desirable. Additionally, knowledge of ASIC design flows and physical design methodologies will be beneficial for this role. Having design-level knowledge to optimize the implementation for Power, Performance, and Area (PPA) will be considered a plus. Qualcomm believes in equal opportunities and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to Qualcomm at disability-accommodations@qualcomm.com or through the toll-free number available on their website.,

As the owner of Ethernovia's India digital hardware team, you will be responsible for all aspects of digital design and digital verification. This position requires both hands-on technical contribution as well as managerial and technical leadership. You will hire and build your own team to plan and execute the design, verification, and validation of advanced automotive communication semiconductors and systems. Key Qualifications: - BS and/or MS in Electrical Engineering, Computer Science, or related field - Minimum 15+ years combined of ASIC design, verification, and leadership experience - Strong understanding of ASIC design and verification fundamentals and industry standard methodologies - Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++ - Experience with the full verification flows, from spec to coverage analysis to gate level sims with SDF - Experience with all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals - Successful track record of leading and growing a digital hardware team - Debugging failures in simulation to root cause problems - Self-motivated and able to work effectively both independently and collaboratively - Startup attitude and expected compensation required Additional Success Factors: - Experience in any of the following areas: Networking (PCIe, Ethernet, MAC, PHY, Switching, TCP/IP, security, and other industry standard protocols), Video standards, protocols, processing, Digital signal processing filters, Third party IP (SerDes, controllers, processors, etc.), Modular and Reusable Testbench architecture, Design for re-use of pre and post-silicon tests and infrastructure, Automation of testbench creation, tests, regression, or EDA tools, Knowledge of SystemC and/or DPI Personal Skills: - Excellent communication/documentation skills - Attention to details - Collaboration across multidisciplinary and international teams What you'll get in return: - Technology depth and breadth expansion that can't be found in a large company - Opportunity to grow your career as the company grows - Pre-IPO stock options - Cutting-edge technology - World-class team - Competitive base salary - Flexible hours - Flexible vacation time to promote a healthy work-life balance,

Skills: ENOVIA V6, CAD Integration, PLM Implementation, 3DEXPERIENCE Platform, MQL Scripts TCL PROGRAMMING JPOs 3D Experience, Web Services based integration architecture, Associate / Lead, Enovia CAD Integration Job Description Summary Job Description Summary Participate in design workshops, involve in design discussions, provide technical inputs and help decision making Analyze the business requirements and translate into IT requirements Review user stories and provide IT specific details and address business questions Execute systems integration test cases and identify issues, if any Test the data flow and integration with existing PLM BOM/Chg mgmt. modules Review technical design and code to address design issues / risks Review the technical solutions with architects and make sure the solution fits to the business and IT needs Develop IT test cases for the functional features testing Champion Enovia PLM integration like CAD Integration, SAP Integration, etc. and its interplay with existing module like BOM Mgmt. and Change Mgmt. Work with Project Manager(s) and business and provide required updates Work Shift Swing Shift (India) Job Description/Preferred Qualifications Job Description/Preferred Qualifications 3-5 years of working experience in developing and configuring solutions on Enovia 3DExperience platform Working experience on CAD Integrations with Enovia PLM, major CAD / PDM systems like Creo/ PDMLink, SolidWorks/EPDM, Inventor Vault, Solid Edge, etc. Working experience on Enovia CAD integration technologies like PowerBy, XPDM architectures and related Working experience of 3DExperience Enovia data model (Classic and UPS) Working experience in UPS data model & 3D Visualization and related 3DExperience apps like Product Structure, 3D Visualization, 3D Issue & Markups, 3D Play, etc. Experience in CAD data migrations is a plus Working experience in Web-services based integration architecture Experience in MQL scripts and TCL programming, JPOs, 3D Experience web and widget development Familiarity with databases such as Oracle and proficiency in SQL Strong written and oral communication skills and solution presentation capabilities Good Problem-solving attitude with analytical skills Minimum Qualifications Minimum Qualifications Doctorate (Academic) Degree and 0 years related work experience; Master's Level Degree and related work experience of 3 years; Bachelor's Level Degree and related work experience of 5 years KLA is a global leader in diversified electronics for the semiconductor manufacturing ecosystem. Virtually every electronic device in the world is produced using our technologies. No laptop, smartphone, wearable device, voice-controlled gadget, flexible screen, VR device or smart car would have made it into your hands without us. KLA invents systems and solutions for the manufacturing of wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel displays. The innovative ideas and devices that are advancing humanity all begin with inspiration, research and development. KLA focuses more than average on innovation and we invest 15% of sales back into R&D. Our expert teams of physicists, engineers, data scientists and problem-solvers work together with the worlds leading technology providers to accelerate the delivery of tomorrows electronic devices. Life here is exciting and our teams thrive on tackling really hard problems. There is never a dull moment with us. Minimum Qualifications Doctorate (Academic) Degree - 0 years related work experience or Master's Level Degree and related work experience of 3 years or Bachelor's Level Degree and related work experience of 5 years 3-5 years of working experience in developing and configuring solutions on Enovia 3DExperience platform CAD Integration Expertise X-CAD and XPDM architecture knowledge. UPS Data Model Strong understanding of Unified Product Structure in Enovia. OOTB App Knowledge Familiarity with 3DPlay, Product Structure, etc. Enovia Development Proficiency in JPOs and JSPs. Functional Configuration Experience in Enovia configuration. Only installation/support wont work. IMMEDIATE REQUIREMENT

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of Hardware Engineering experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 5+ years of Hardware Engineering experience OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering experience Responsibilities: - 5 to 10 years of experience in static timing analysis, constraints, and other physical implementation aspects - Proficiency in industry standard tools PT, Tempus, GENUS, Innovus, ICC, etc. - Expertise in solving extreme critical timing bottleneck paths and preparing complex ECOs for timing convergence - Knowledge of minimizing power consumption and experience in deep submicron process technology nodes - Understanding of high performance and low power implementation methods - Strong fundamentals and expertise in Perl, TCL language - Willingness to optimize power, performance, and area to the best possible extent Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodation during the application/hiring process, please contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Note to Staffing and Recruiting Agencies: Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing agencies and their represented individuals are not authorized to submit profiles, applications, or resumes through this site. Unsolicited submissions will not be considered, and Qualcomm does not accept resumes or applications from agencies. For more information about this role, please reach out to Qualcomm Careers.,

We are searching for a highly skilled Python Automation Engineer with expertise in 5G networks and IMS (IP Multimedia Subsystem) testing to become a part of our dynamic team. The perfect candidate will have practical experience in automating test scripts, telecom protocol testing, and ensuring the quality, performance, and resiliency of 5G/4G network functions. As a Python Automation Engineer, you will have a significant role in the validation of IMS architecture, automation of test cases, and performance verification of network functions. Your responsibilities will include developing and maintaining automated test scripts utilizing Python, TCL, and BDD to validate IMS functionalities and 5G/4G network features. You will design, execute, and enhance test cases for telecom protocols such as SIP, Diameter, MAP, SBI, RTP, and DNS. Additionally, you will be performing integration, performance, and resiliency testing of IMS applications and 3GPP nodes like HLR, HSS, UDM, SMSC, PGW, SMF, and MME. Building and maintaining automation frameworks to streamline test execution and reporting, conducting manual and automated testing for IMS-based services such as VoLTE, VoWiFi, and RCS, simulating network traffic, and testing performance under various conditions using tools like IxLoad, Landslide, and EXFO are crucial aspects of the role. Furthermore, you will be responsible for debugging and troubleshooting issues at both software and network levels using logs, stats, Grafana, and protocol analyzers like Wireshark. Your collaboration with software engineers, network engineers, and DevOps teams to resolve issues and enhance system performance is essential. Integrating automated tests into CI/CD pipelines using Kubernetes, Flux/GitOps, testing system resiliency, geo-redundancy, hardware failure scenarios, and conducting chaos testing will also be part of your duties. To excel in this role, you must possess strong programming skills in Python, along with experience in TCL and BDD. A solid understanding of IMS and its components (HSS, PCRF, CSCF), practical experience with 5G/4G networks and 3GPP nodes, deep knowledge of telecom protocols (SIP, Diameter, MAP, SBI), experience with automation tools and frameworks like Robot Framework, Selenium, or pytest, proficiency with network simulators and analyzers, hands-on experience with Kubernetes, GitOps (Flux), and CI/CD pipelines, strong networking knowledge, experience in performance/load/stress testing and debugging at scale, familiarity with monitoring tools and bug tracking tools, understanding of telecom standards and IMS-based services, as well as excellent communication skills and ability to work in a collaborative environment, are crucial. In return, we offer a competitive salary and benefits package, a culture focused on talent development, opportunities to work with cutting-edge technologies, employee engagement initiatives, annual health check-ups, and insurance coverage for self, spouse, children, and parents. Persistent Ltd. is committed to fostering diversity and inclusion in the workplace, providing hybrid work options and flexible working hours, and creating an inclusive environment where all employees can thrive. Join us at Persistent and unleash your full potential. Persistent is an Equal Opportunity Employer and prohibits discrimination and harassment of any kind.,

Job Title: Engineer - Network Reliability GCL: C3 Introduction To Role Are you ready to make a difference in a world-leading pharmaceutical company? As a Network Reliability Engineer, you'll be at the forefront of ensuring seamless network operations across continents. With your expertise, you'll support and maintain a robust network infrastructure that powers life-changing medicines. Dive into a dynamic environment where your skills will be pivotal in redefining network connectivity and user experience. Accountabilities Meet delivery targets set by management. Ensure delivery exceeds SLA levels and establish processes for continuous service improvement. Support, maintain, and enhance user experience in network connectivity. Deliver accurate, timely diagnosis and rectification of network faults. Monitor network events using world-class tools and address alert incidents. Resolve or advance incidents/problems/service requests per established procedures. Track and progress-chase incidents to conclusion in line with SLA and quality standards. Work within an ITIL environment for Change and Incident management. Handle incidents/service requests related to LAN/WAN/Wireless/Firewall/Load balancer/Proxy globally. Collaborate with onsite network engineers/ISP for Layer 1/2 troubleshooting. Prepare network reports for management meetings. Expedite change for incident break fix and implement changes after necessary approvals. Essential Skills/Experience A minimum of a bachelor’s Degree is required, with MS or MBA or equivalent experience preferred. 3-5 years’ experience in Network Operations, Troubleshooting. Proven ability in configuring/administrating Cisco routers, Switches (Cisco/Ruckus), Firewall (ASA/Checkpoint), Netscaler Load balancer, Zscaler Cloud-based proxy. Skills in LAN/Switching: Cisco Catalyst series switches, Cisco VSS technology, Nexus switches. Routing: Policy-based routing, Intelligent WAN (iWAN) technology, Handling Cisco ISR/ASR routers, knowledge in dynamic routing protocols such as BGP, EIGRP/OSPF. Security: Good knowledge in ASA, Checkpoint firewalls, Cisco ZBF, Zscaler. Load balancer: Knowledge of Netscaler/F5 load balancer. Experience in resolving tools like Netbrain or equivalent, NMS tools like Solarwinds, EMC SMARTS, Log analysis tools like Splunk, Kiwi or equivalent. Ready to work in rotational shift. Good communication skills, both written and verbal, with excellent presentation skills. Desirable Skills/Experience Strong routing knowledge/Firewall devices from ISP environment preferred. Experience in scripting languages like Python, Perl, TCL or others is an advantage. Understanding of Network Automation & Low code Automation platforms such as Itential is an advantage. Good knowledge of Incident Management/Change management/Problem Management processes. Experience working in globally distributed teams. Knowledge in ticketing systems like Remedy, SNOW. CCNA (R/S or Security) certification required. CCNP/CCSA/CCSE and ITIL certifications are added advantages. Ability to grasp and understand new technological trends/concepts. Must possess good problem-solving and interpersonal skills. Must excel working in team environments. When we put unexpected teams in the same room, we ignite bold thinking with the power to inspire life-changing medicines. In-person working gives us the platform we need to connect, work at pace and challenge perceptions. That's why we work, on average, a minimum of three days per week from the office. But that doesn't mean we're not flexible. We balance the expectation of being in the office while respecting individual flexibility. Join us in our unique and bold world. At AstraZeneca, you'll be part of a team that redefines the industry and changes lives. Our work directly impacts patients by redefining our ability to develop life-changing medicines. We empower the business to perform at its peak by combining ground breaking science with leading digital technology platforms and data. With a passion for data, analytics, AI, machine learning, and more, you'll be at the heart of driving cross-company change to deliver exponential growth. Join us at a crucial stage of our journey to become a digital and data-led enterprise. Ready to take the next step? Apply now and be part of our innovative journey! Date Posted 21-Jul-2025 Closing Date AstraZeneca embraces diversity and equality of opportunity. We are committed to building an inclusive and diverse team representing all backgrounds, with as wide a range of perspectives as possible, and harnessing industry-leading skills. We believe that the more inclusive we are, the better our work will be. We welcome and consider applications to join our team from all qualified candidates, regardless of their characteristics. We comply with all applicable laws and regulations on non-discrimination in employment (and recruitment), as well as work authorization and employment eligibility verification requirements.