Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Dassault Systemes ENOVIA V5 Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will be responsible for developing and configuring software systems either end-to-end or for a specific stage of the product lifecycle. You will apply knowledge of technologies, applications, methodologies, processes, and tools to support a client, project, or entity. Your role involves leading software development projects and ensuring their successful completion. Key responsibilities-1.Knowledgeable in Testing and Deployment concepts.2.Creating & recording of test cases and preparation of test data in 3DExperience Catia3. Review the test plans, test cases and validate the test results5. Ability to completely own and support unit and integration testing6. Awareness of testing concepts - white box and black box. Professional & Technical Skills: 1. Experience on 3DExperience CATIA 2020x or above in functional testing.2. Experience of testing concepts, STLC and methodologies.3. Experience on Configuration and variant management4. 3DExperience CATIA Functional Knowledge 5. Knowledge of Test Automation and scripting language.6. Agile way of project working experience.7. Experience in 3DExperience CATIA.8. Outstanding all-round communication skills and ability to work collaboratively8. Should be a team player Additional Information:- The candidate should have minimum 6+ years' Experience on 3DExperience CATIA 2020x or above in functional testing.- This position is based at our Bengaluru office.- A 15-year full time education is required. Qualification 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Dassault Systemes 3DEXPERIENCE ENOVIA Customization Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various stakeholders to gather requirements, overseeing the development process, and ensuring that the applications meet the specified needs. You will also engage in problem-solving discussions, providing insights and solutions to enhance application functionality and user experience. Additionally, you will mentor team members, fostering a collaborative environment that encourages innovation and continuous improvement. Roles & Responsibilities:Coordinate with customers to perform data cleansing on the source system and import/save the cleaned SolidWorks data into the 3DEXPERIENCE platform.Understand and work with SolidWorks configurations and data structures relevant to migration.Validate imported data in the latest versions of the 3DEXPERIENCE platform to ensure accuracy and completeness.Develop or execute scripts using TCL and MQL for data correction, transformation, and automation.Collaborate with cross-functional teams to ensure end-to-end data migration quality and success.Document data migration procedures, challenges, resolutions, and validation results. Professional & Technical Skills: Strong understanding of SolidWorks and its configuration settings related to data migration.Hands-on experience with latest versions of 3DEXPERIENCE platform, especially in data validation workflows.Proficiency in scripting using TCL and MQL.Ability to work closely with business stakeholders and technical teams to ensure clean and complete data migration.Good to Have skills- Familiarity with ETL tools such as SSIS or equivalent.Exposure to relational databases like Microsoft SQL Server and MySQL.Experience in consuming and integrating with RESTful web services for data load operations. Additional Information:- The candidate should have minimum 4+ years of experience in Dassault Systemes 3DEXPERIENCE ENOVIA Customization.- This position is based at our Chennai office.- A 15 years full time education is required. Qualification 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Dassault Systemes 3DEXPERIENCE ENOVIA Customization Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various stakeholders to gather requirements, overseeing the development process, and ensuring that the applications meet the specified needs. You will also engage in problem-solving discussions, providing insights and solutions to enhance application functionality and user experience. Additionally, you will mentor team members, fostering a collaborative environment that encourages innovation and continuous improvement. Roles & Responsibilities:1. Guiding the team in development / customization using Enovia data migration.2.Understands and develops software solutions to meet end user's requirements. Ensures that applications integrate with overall system architecture, utilizing standard IT lifecycle methodologies and tools.3. Should be responsible to handle design, development, and analysis and Delivery of the requirements. Professional & Technical Skills: - Must Have Skills: 3DEXPERIENCE 2019x widget and dashboard, 3DEXPERIENCE 2019x Data Migration1.Hands-on experience with latest versions of 3DEXPERIENCE platform, especially in data validation workflows.2.Proficiency in scripting using TCL and MQL.3. Experienced in Widget customization, webservices.4. Matrix services knowledge, xPDM xml to Enovia data mapping knowledge.- Good to Have Skills: Enovia 2019x Program, Variant, and Change Management, Familiarity with ETL tools such as SSIS or equivalent. Additional Information:- The candidate should have minimum 4+ years of experience in 3DEXPERIENCE 2019x or above customization and configuration.- This position is based at our Hyderabad office.- A 15 year full time education is required. Qualification 15 years full time education

Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Dassault Systemes 3DEXPERIENCE ENOVIA Customization Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will be responsible for developing and configuring software systems, applying knowledge of technologies, methodologies, and tools to support projects or clients throughout the product lifecycle. Roles & Responsibilities:- Expected to be an SME- Collaborate and manage the team to perform- Responsible for team decisions- Engage with multiple teams and contribute on key decisions- Provide solutions to problems for their immediate team and across multiple teams- Lead the team in developing and configuring software systems- Implement methodologies and processes to support project objectives Professional & Technical Skills: - Must To Have Skills: Proficiency in Dassault Systemes 3DEXPERIENCE ENOVIA Customization- Strong understanding of software development lifecycle- Experience in end-to-end software system development- Knowledge of technologies and applications in software development Additional Information:- The candidate should have a minimum of 5 years of experience in Dassault Systemes 3DEXPERIENCE ENOVIA Customization- This position is based at our Bengaluru office- A 15 years full time education is required Qualification 15 years full time education

Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Dassault Systemes 3DEXPERIENCE ENOVIA Customization Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will be responsible for developing and configuring software systems, applying knowledge of technologies, methodologies, and tools to support projects or clients throughout the product lifecycle. Roles & Responsibilities:- Expected to be an SME- Collaborate and manage the team to perform- Responsible for team decisions- Engage with multiple teams and contribute on key decisions- Provide solutions to problems for their immediate team and across multiple teams- Lead and mentor junior professionals- Drive innovation and continuous improvement within the team Professional & Technical Skills: - Must To Have Skills: Proficiency in Dassault Systemes 3DEXPERIENCE ENOVIA Customization- Strong understanding of software development lifecycle- Experience in system configuration and customization- Knowledge of technologies and tools for software development- Ability to troubleshoot and resolve technical issues Additional Information:- The candidate should have a minimum of 5 years of experience in Dassault Systemes 3DEXPERIENCE ENOVIA Customization- This position is based at our Bengaluru office- A 15 years full time education is required Qualification 15 years full time education

Project Role : Engineering Services Practitioner Project Role Description : Assist with end-to-end engineering services to develop technical engineering solutions to solve problems and achieve business objectives. Solve engineering problems and achieve business objectives using scientific, socio-economic, technical knowledge and practical experience. Work across structural and stress design, qualification, configuration and technical management. Must have skills : Dassault Systemes 3DEXPERIENCE ENOVIA Customization Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Engineering Services Practitioner, you will assist with end-to-end engineering services to develop technical engineering solutions, solve problems, and achieve business objectives. You will work across structural and stress design, qualification, configuration, and technical management, utilizing scientific, socio-economic, technical knowledge, and practical experience. Roles & Responsibilities:- Expected to perform independently and become an SME.- Required active participation/contribution in team discussions.- Contribute in providing solutions to work-related problems.- Develop innovative engineering solutions to address complex challenges.- Collaborate with cross-functional teams to ensure project success. Professional & Technical Skills: - Must To Have Skills: Proficiency in Dassault Systemes 3DEXPERIENCE ENOVIA Customization.- Strong understanding of engineering principles and practices.- Experience in technical project management.- Knowledge of CAD software and design tools. Additional Information:- The candidate should have a minimum of 3 years of experience in Dassault Systemes 3DEXPERIENCE ENOVIA Customization.- This position is based at our Pune office.- A 15 years full-time education is required. Qualification 15 years full time education

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute The SVT/PV Engineer will develop test strategies, automation script development, and execute test plans for Ciena’s Packet Optical products, focusing on OTN Transport, Switching, Automation and NMS. Key Responsibilities Develop, automate and execute test strategies for Telecom networks. Create and execute test plans using Manual and Automation methods. Identify and automate test scenarios. Debug and resolve defects with design teams. Ensure compliance with industry standards (ITU-T, IETF, IEEE, ANSI). Must Have OTN Transport & Switching Test Automation (TCL/Python) Defect Analysis & Debugging Telecom Network Testing with hands-on experience with Test Equipment’s. Bachelor’s/Master’s in Electronics, Computer Science, or Optical Communications. 5+ years in Telecom System Testing. Experience in test planning/execution, automation, reporting and debugging. Exposure to photonics/DWDM, NMS and TDM/packet technologies Improved test efficiency & automation coverage Reduction in defect leakage & debugging time Compliance with test quality standards Nice-to-Have Skills Exposure to different NBIs – REST, NETCONF, gRPC and Photonics/DWDM Exposure to photonics/DWDM, NMS and TDM/packet technologies Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3074284 Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3074283 Show more Show less

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. Candidate will be responsible for integration testing of POTS platform and releases. Testing will include understanding of platform, features, generating test plans, execution of of tests and automation of test cases for regression. Essential Duties And Responsibilities Understand - platforms and features to test, supported feature requirements Develop test plan, review the plan with design and execute the test cases on corresponding releases. Understand automation framework and automate the test cases Verify the automated suites and run the suites for regression & sanity Build in-depth knowledge of product architecture and develop ability to root-cause issue Minimum Qualifications Bachelor degree in Computer Science, similar technical field of study Hands on Experience in Optical OTN and TDM technologies : Functional, System, Performance and Scale Hands-on Experience Needed For The Following Testing Experience in Optical Domain including OTN (G.709), SONET/SDH, DWDM, TDM Synchronizing Principles Good working knowledge of OTN Standards including OTN G.709 , G.7710..etc.. Experience in OTN traffic generators is essential – ONT/VIAVI, EXFO, Tberd, IXIA(IxNetwork/IxExplorer) Automation experience in TCL or Python Understanding of L2/L3 &MPLS technology with exposure in routing & switching is good to have i.e.ISIS ,MPLS, RSVP. Experience in both Manual and Automated testing environments is required Understanding of Waterfall & Agile models of development Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Show more Show less

About The Role As a Staff DevOps Engineer focused on Site Reliability within Infrastructure Engineering and Cloud Operations (IECO), you will contribute to the development of our solution delivery platforms supporting our web-based applications on the latest cloud technologies within a DevSecOps culture. You will have the opportunity to utilize automation technologies and private/public cloud technologies to provide world-class solutions that serve the non-profit industry. What You'll Do Build automation leveraging CI/CD processes, automated testing, unit testing, code coverage and other software development best practices Contribute to reusable automation scripts, libraries, services, and tools to increase system and process efficiencies Partnering with the security teams and tools to continually review and understand new industry security threats, associated technologies and quickly addressing vulnerabilities Pursue opportunities to further operational excellence by increasing efficiency and reducing risk, complexity, waste and cost Partner with key stakeholders to establish technical direction and negotiate technical decision points to drive innovative solutions Drive technical design and validation, while ensuring implementation aligns with our technical strategies and strategic business goals Develop architectural designs for applications building something to delight clients while managing costs to deliver these applications What You’ll Bring 2+ years of experience with common web technologies required – Javascript, C#, .NET, HTML, AJAX or other equivalent Object-Oriented language 2+ years of experience in the implementation of cloud technologies (Microsoft Azure) and an understanding of SAAS, PAAS, and IAAS models Experience building high performance, scalable, robust, 24x7 environments and/or applications Experience creating scripts or automation, such as Perl, PowerShell, Python, TCL/TK, Ruby or similar for cloud orchestration required (PowerShell preferred) Available on a 24x7x365 basis when needed for production impacting incidents or key customer events Ability to develop quality code that is secure and operable at scale Stay up to date on everything Blackbaud, follow us on Linkedin, X, Instagram, Facebook and YouTube Blackbaud is a digital-first company which embraces a flexible remote or hybrid work culture. Blackbaud supports hiring and career development for all roles from the location you are in today! Blackbaud is proud to be an equal opportunity employer and is committed to maintaining an inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, physical or mental disability, age, or veteran status or any other basis protected by federal, state, or local law. R0012482 Show more Show less

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X) . Principal Engineer, Design Verification The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Digital Systems IP team within the Engineering Enablement organization. The IP team builds, curates and guides the development of IP across ADI. We’re seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for verification of different IP components, subsystems from scratch. About the role In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation, and release of IP to various product teams. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career. Responsibilities Verification of complex Digital designs and sub-systems using leading edge verification methodologies. Architecting a unified verification testbench environment Defining verification strategy, testplans, tests and verification methodology for chip-level verification. Working with the design team in generating test-plans and closure of code and functional coverage Technically mentoring verification engineers on SoC Verification responsible for block/IP-level DV Continuous interaction with Design, Architecture and Firmware teams Tracking and management of design verification improvements Required Qualifications Bachelor's or Master’s degree, in Engineering (Electronic Engineering) or equivalent. 15 years ASIC design verification or related work experience. Leadership skills enabling one to define and implement a verification strategy Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications Proficient in developing unit and SoC level test benches using UVM Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology, formal verification Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium Working with processors Gate Level Simulation (GLS) verification flow for SoC verification. Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting Experience in Property Specification Language (PSL), Matlab (including for co-simulation and HDL generation) and digital signal processing would be a plus Low power methodologies such as CPF/UPF Excellent interpersonal and communication skills and the dream to take on diverse challenges Self-motivated and enthusiastic For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74460 Job Description Summary: Digital design engineer developing complex mixed-signal ICs for frequency control, clock generation, network synchronization, and other timing applications. Candidate will take a supporting or leading role depending on experience relative to other team members, but regardless of experience level, candidate will be involved in all aspects of the design process from system conceptualization to mass production. For example, candidate will participate in digital system architecture, block- and system-level RTL design/coding, algorithm and firmware development, digital circuit back-end (e.g. synthesis, timing closure, P&R preparation, scan insertion), firmware development (some ICs include embedded processors), digital design verification, and full-chip mixed-signal verification. Responsibilities will also include detailed documentation, test vector development, lab test and evaluation, customer support, and other activities as required for the achievement of high volume production. Responsibilities: Digital design specification, design, analysis, and HDL (Verilog) coding Behavioral modeling of analog and mixed signal circuits Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc. Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development Validation of silicon functionality, behavior, and performance Job Requirements Master's with 7-10 years of IC design experience or PhD with 4-6 years of IC design experience Strong motivation to contribute to all facets of chip design from conceptualization to release to production Working knowledge of digital IC circuit design in an HDL synthesis environment Working knowledge of digital verification and testing techniques Good verbal and written communication skills, positive attitude, desire to learn, and willingness to work on a team Working knowledge of UNIX operating systems Additional skills (one or more of these are highly desirable): Experience with digital design at geometries ranging from 130-40 nm Experience with digital IO interfaces such at I2C, SPI, etc. Competence in high-level languages (e.g. Matlab, C), scripting languages (e.g. Tcl, Perl, Python, SKILL), and version control systems (e.g. SVN, SOS) Working knowledge of System Verilog and/or UVM Experience leading a team of digital designers, either formally or informally Experience with embedded processor design and firmware/software development, especially for 8051 or ARM cores Competence in exploring digital and firmware system/architecture trade-offs such as memory size (ROM, RAM, FLASH, OTP, cache), clock speed, multiple clock domains, and the necessity for dedicated logic and DSP Experience with memory generators and MBIST Low power design and implementation techniques Familiarity with DSP techniques and algorithms Experience with Phase-locked-loops, Frequency Synthesizers or CDR circuits. Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL - DFT Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: The person is responsible for ensuring the integrity of a design by analyzing signal connectivity, specifically related to Design for Testability (DFT) features, utilizing Spyglass tools to identify and report potential violations within the test logic. Required Skills: Expertise should include and not limited to the following Strong understanding of digital circuit design principles and timing analysis concepts Experience with RTL design, synthesis Proficiency in scripting languages like TCL, Perl, or Python for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities to collaborate with cross-functional teams TekWissen® Group is an equal opportunity employer supporting workforce diversity. Show more Show less

Introduction As a Hardware Developer at IBM, you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market. Your Role And Responsibilities We are seeking highly motivated Test engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, delivery of DFT patterns and testing the patterns for IBM’s microprocessor chip design team. Preferred Education Master's Degree Required Technical And Professional Expertise 4–9 years of experience in ATE test development, silicon debug, and production support for complex SoC or ASIC devices. Strong expertise in test program development, test vector translation, timing setup, and ATE bring-up workflows. Proven ability in debugging test failures, analyzing yield and parametric issues, and resolving silicon bring-up and characterization challenges. Experience with RMA debug – reproducing, analyzing, and isolating failures in customer-returned or field-returned silicon. Hands-on experience with PVT (Process, Voltage, Temperature) characterization, using ATE. Experience in pattern generation, pattern retargeting, and vector-level debug using standard ATE tools (e.g., Teradyne, Advantest). Strong knowledge of pin margin analysis, voltage/timing margining, and correlation between simulation and ATE results. Proficient in automation and scripting using VB (Visual Basic), Perl, Python, and TCL for test flow automation, log parsing, and pattern manipulation. Effective collaboration with cross-functional teams including design, validation, product engineering, and silicon debug to ensure test robustness and quality. Excellent debug and bring-up skills – considered key requirements for this role. Detail-oriented with solid analytical and problem-solving abilities. Strong communication skills and ability to work across global teams. Preferred Technical And Professional Experience Experience with Teradyne UltraFlex (UFlex) tester is a plus. Familiarity with microcontroller architecture, embedded firmware, and functional verification concepts. Experience in post-silicon validation, system-level debug, and yield optimization workflows. Knowledge of processor-based test flows, scan diagnostics, and test time optimization Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and passionate individual with a strong background in semiconductor manufacturing technology and device physics. You hold a PhD in Electrical Engineering or Physics and have a deep understanding of numerical methods. You possess excellent IT skills, particularly in Linux as well as Python and TCL scripting. With at least three years of experience using TCAD simulation tools, you are adept at both pre-sales and post-sales activities, including technical support, customer relationship management, technical training, and presentation delivery. You thrive in a dynamic environment, working closely with R&D, Sales, Marketing, and customers to drive the development and acceptance of cutting-edge TCAD products. What You’ll Be Doing: Serving as the primary technical interface with customers, assisting them in evaluating, using, and applying TCAD tools. Providing technical support, troubleshooting, and resolving complex issues related to TCAD products. Managing new and existing customer relationships, ensuring high levels of customer satisfaction. Preparing and delivering technical training and presentations to customers and internal teams. Conducting beta testing, benchmarking, and onsite evaluations to support product development and customer needs. Collaborating with R&D to specify new features and drive continuous product improvement. The Impact You Will Have: Enhancing customer experience and satisfaction with Synopsys TCAD products. Driving the successful adoption and integration of TCAD tools in leading semiconductor companies. Contributing to the development and refinement of state-of-the-art TCAD tools. Strengthening Synopsys' market position through exceptional technical support and customer engagement. Facilitating knowledge transfer and training to empower customers and internal teams. Playing a key role in the continuous innovation and advancement of semiconductor technology. What You’ll Need: PhD in Electrical Engineering, Physics, or a related field. Strong background in semiconductor manufacturing technology and device physics. Proficiency in numerical methods and simulation tools. Excellent IT skills, particularly in Linux, Python, and TCL scripting. Minimum of three years of experience with TCAD simulation tools. Who You Are: A proactive and customer-oriented professional with excellent communication skills. Detail-oriented with strong problem-solving abilities. A collaborative team player who thrives in a dynamic environment. Adaptable and able to manage multiple priorities effectively. Passionate about technological innovation and continuous learning. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on driving the development and adoption of Synopsys TCAD products. Collaborating closely with R&D, Sales, Marketing, and customers, you will play a crucial role in ensuring the success and continuous improvement of our cutting-edge semiconductor technology solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled engineer with 6-10 years of experience, passionate about developing cutting-edge emulation solutions for industry-standard protocols such as PCIe, CXL, and UCIe. You possess a strong background in software development using C/C++ and synthesizable RTL development with Verilog. Your deep understanding of digital design concepts, HDL languages, and scripting languages like Python or Perl will be invaluable in this role. You thrive in collaborative environments, have excellent communication skills, and are adept at solving complex problems. Your ability to interact with customers during deployment and debug processes will ensure successful implementation and satisfaction. A B.E/B.Tech/M.Tech in Electronic & Communication or Computer Science Engineering is essential. Knowledge of ARM architecture, UVM, and functional verification, along with experience in emulation, will be a significant advantage. What You’ll Be Doing: Developing emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth implementation. Collaborating with cross-functional teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: Driving the development of advanced emulation solutions that meet industry standards. Enhancing the performance and reliability of semiconductor products through innovative solutions. Ensuring customer satisfaction by providing robust and efficient deployment support. Contributing to the continuous improvement of Synopsys' emulation technologies. Supporting the adoption of new protocols and standards in the semiconductor industry. Strengthening Synopsys' position as a leader in chip design and verification solutions. What You’ll Need: 5+ years of relevant experience In-depth knowledge of PCIe, CXL, and UCIe protocols. Proficiency in C/C++ programming and object-oriented programming concepts. Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog. Experience with scripting languages like Python, Perl, or TCL. Familiarity with ARM architecture and UVM/functional verification is a plus. Who You Are: A collaborative team player with excellent communication skills. A problem-solver with a keen eye for detail and a passion for innovation. Adaptable and able to work effectively in a fast-paced, dynamic environment. Customer-focused, with the ability to handle deployment and debugging challenges efficiently. Committed to continuous learning and staying updated with industry advancements. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing and enhancing emulation solutions for cutting-edge semiconductor technologies. Our team collaborates closely with various departments to ensure the highest quality and performance of our products, driving innovation and excellence in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

🚀 About the Role We're hiring an experienced FPGA Firmware Engineer to develop and integrate high-speed digital systems for cutting-edge defence and aerospace applications. You'll work on complex RTL logic, high-speed interface protocols like 10G Ethernet and JESD204B/C, and mentor junior engineers in a mission-critical development environment. If you’re passionate about FPGA design and want to contribute to indigenous strategic technologies, we’d love to meet you. 📍 Location : Chennai | 🕒 Full-Time | 🧭 Experience : 3–5 Years No. of Vacancy : 01 🎯 What You’ll Do Design and implement RTL code (VHDL/Verilog) for FPGA-based systems (Xilinx/Intel). Integrate and validate 10G Ethernet, JESD204, and AXI-based IP cores. Collaborate with hardware teams for board bring-up and system-level debugging Optimise firmware for high-speed data processing, signal acquisition, and control loops. Simulate, verify, and debug designs using tools like Vivado, ModelSim, and Logic Analysers. Mentor a team of junior engineers and ensure adherence to coding standards. Contribute to documentation and compliance (DO-254, AS9100). Interface with cross-functional teams, including QA, hardware, and system engineering. ✅ What We’re Looking For B.E./ B.Tech or M.E./ M.Tech in ECE, EE, or related fields. 3–8 years of FPGA development experience in defence/aerospace or high-reliability domains. Hands-on experience with Vivado/Quartus, ModelSim/QuestaSim, and constraint-based timing closure. Strong understanding of 10G Ethernet, JESD204B/C, CDC, and high-speed digital design. Proficiency in scripting (Tcl, Python) and hardware debugging tools. Experience working with embedded soft cores (MicroBlaze, Zynq, or Nios II) is a plus. Team leadership or mentoring experience preferred. 🌐 Nice to Have Worked on radar, EW, or signal processing systems. Familiarity with MIL-STD, ARINC 818, or custom defence protocols. Prior engagement with DRDO, BEL, HAL, or Indian defence projects. 🛡 Why Join Us Work on indigenous, mission-critical defence systems. Be part of a growing high-tech R&D environment. Get opportunities to lead, innovate, and mentor. Secure and process-driven workplace with a focus on national development. Tips: Provide a summary of the role, what success in the position looks like, and how this role fits into the organisation overall. 📩 Apply Now If you're ready to take the lead on high-performance FPGA systems and mentor the next generation of engineers, apply now or send your profile to admin@indrainsignia.co.in Show more Show less

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. www.silabs.com Meet the team: The Baseband Modem Design group, in HYD, is primarily responsible for designing and developing cutting-edge WIFI modem solutions which are integrated into low-power/line-powered SoCs used in Wireless-IOT products. The group is responsible for the RTL implementation of the new WIFI standards required in the IOT space market. The team actively collaborates with signal processing experts in defining the algorithms and implementing them. The team also verifies core modem functionality and works with extended Verification team to verify all the System level usecases involving the baseband modem. It also handles the pre-Si and post-Si validation. Responsibilities: Develop complex communications or signal processing blocks for wireless-IOT products. Understanding of OFDM/signal processing is strongly desired Collaborate with System Engineers to drive the definition of wireless blocks to meet product requirements. Proficiency in Matlab/C is strongly preferred Micro-architecture and RTL design of modules using Verilog/System Verilog HDL coding, adhering to quality standards. Prepare and hold Architecture, Design, and Verification reviews with technical staff throughout project lifecycle Pre-silicon verification utilizing a combination of block/chip-level test benches. Validation/bring-up of designs on silicon, providing support to cross-functional teams Apply Low-power digital circuit design concepts Skills required: Demonstrated ability to work with Systems team to micro-architect and design complex digital subsystems Understand Matlab algorithm implementation and translate to effective RTL micro-architectures Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to production Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers (like vc, Questasim), and power analysis tools Experience with logic synthesis, timing constraints and timing closure Experience in working with backend team to optimize design for power performance and area Experience with scripting and automation. Knowledge of Python, Perl, and Tcl Experience with revision control and configuration management systems (such as Perforce, Git, Methodics) Excellent written and verbal communications skills Demonstrated ability to generate high output in a self-driven manner Experience Level: 4-6 years in Industry Education Requirements: Master’s /Bachelors degree in Communications/Electronics Engineering Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law. Show more Show less

Physical Design Engineer (PD/STA/Synthesis) Must-Haves: • Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA • Flow Experience: • Floorplanning • Power planning • Placement • Clock Tree Synthesis (CTS) • Routing • Physical Verification (DRC/LVS) • Timing Closure • Knowledge of: • Low-power design (UPF/CPF) • ECOs • IR Drop, EM Analysis • STA constraints and timing analysis Nice-to-Haves: • Experience with block-level and/or full-chip PD • Familiarity with scripting (Tcl, Perl, Python) Show more Show less

Senior Staff Physical Design Engineer - STA Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background Introducing The Information’s 50 Most Promising Startups for 2024 We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Full Time \ Experienced Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device. Roles and Responsibilities Perform STA (static timing analysis) at block/full-chip level Specify timing ECOs either manually or via a tool-generated flow Perform noise analysis at the block/full-chip level Develop and debug timing constraints Define and implement MCMM (multi corner, multi-mode) timing closure methodology Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications : Proficient in STA tools like Tempus, Tweaker, and PrimeTime Proficient in programming languages like Tcl, python, etc. Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR Strong understanding of LVF/OCV variation methodologies and their implementation Knowledge of timing convergence in multi-voltage scenarios Working knowledge using timing derates and implementing timing derates into the flows Minimum BSEE/CE + 12 years or MSEE/CE 10+ years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Senior Principal / Principal / StaffPhysical Design Engineer - STA Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background Introducing The Information’s 50 Most Promising Startups for 2024 We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Full Time \ Experienced Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device. Roles and Responsibilities Perform STA (static timing analysis) at block/full-chip level Specify timing ECOs either manually or via a tool-generated flow Perform noise analysis at the block/full-chip level Develop and debug timing constraints Define and implement MCMM (multi corner, multi-mode) timing closure methodology Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications : Proficient in STA tools like Tempus, Tweaker, and PrimeTime Proficient in programming languages like Tcl, python, etc. Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR Strong understanding of LVF/OCV variation methodologies and their implementation Knowledge of timing convergence in multi-voltage scenarios Working knowledge using timing derates and implementing timing derates into the flows Minimum BSEE/CE + 12 years or MSEE/CE 10+ years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

ASIC/SOC Front End Design Engineer Job description: 1. Setup ASIC QA flows for RTL design quality checks. 2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. 3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. 4. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. 5. Checking the flow errors, design errors & violations and reviewing the reports. 6. Debugging CDC, RDC issues and come up with the RTL fixes. 7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. 8. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. 9. Flows or Design porting to different technology libraries. 10. Generating RAMs based on targeted memory compilers and integrating with the RTL. 11. Running functional verification simulations as needed. Job Requirements: 1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience 2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes 3. Modern SOC tools including Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, VCS simulation 4. Experience in signoff of front end quality checks & metrics for various milestones of the project 5. TCL, Perl, Python scripting Experience: 3 to 5 years Location: Hyderabad Notice Period: Immediate Show more Show less