1570 Tcl Jobs - Page 12

Role Overview: The MIS Head will be responsible for controlling, driving and monitoring the company’s Management Information Systems (MIS) to ensure accurate, real-time business intelligence for decision-making. This role requires expertise in all MIS tools, team leadership and the ability to drive performance of MIS team. The candidate should have the latest knowledge in data analytics, reporting automation and business intelligence to enhance operational efficiency and profitability. Key Responsibilities: Develop and execute a comprehensive MIS strategy aligned with business goals. Ensure seamless data collection, processing, validation and reporting for informed decision-making. Lead, control, and drive a team and ensuring high performance. Set KPIs and performance metrics for the MIS team and ensure targets are met. Conduct regular training and upskilling sessions to keep the team updated with the latest MIS trends. Leverage Power BI, Tableau, SQL, Python, and AI-driven analytics for data-driven decision-making. Develop automated dashboards, reports and forecasting models to provide real-time business insights. Automate data flow between different business functions for increased efficiency. Provide Daily/weekly/monthly business performance reports to senior management. Analyze market trends, sales forecasts, and operational bottlenecks to suggest improvements. Qualifications & Experience: Bachelor’s/Master’s degree in MIS, IT, Data Analytics, Business Administration, Finance, or related fields. Certifications in Power BI, SQL, Tableau, Python, AI-Driven Analytics, or ERP systems are preferred. 3+ years of experience in MIS, Data Analytics, or Business Intelligence. Proven track record of leading MIS teams and driving high performance. Expertise in handling large-scale data and implementing automation. Excellent analytical and problem-solving skills. About Company : Alps Distribution is the only authorized distributor of Apple products in Kerala and Tamil Nadu, headquartered in Cochin with branches in Trivandrum, Thrissur, Calicut, Chennai, Coimbatore, Madurai, and Trichy. Alps Distribution holds the number one position for Apple products distribution in India. Aldous Glare Tech & Energy (AGTE) is a subsidiary of Alps. Aldous Glare is India’s leading distributor for smartphones (Vivo), TCL - Android TVs, Google TVs, smart ACs, smart washing machines and Solar Products. For 30 years now, Aldous Glare Tech & Energy have stood the test of time and established ourselves as a brand synonymous with trust and quality. Technology and its advancements are ubiquitous and we function with the prime goal of increasing accessibility, awareness of the latest tech gadgets and appliances. We creates opportunities for its channel partners through aggressive market development and continuous improvements through agility. Company Website : www.aldousglare.com & www.alpsd.com Job Types: Full-time, Permanent Pay: ₹35,000.00 - ₹40,000.00 per month Benefits: Cell phone reimbursement Health insurance Leave encashment Provident Fund Schedule: Day shift Fixed shift Morning shift Supplemental Pay: Yearly bonus Ability to commute/relocate: Kochi, Kerala: Reliably commute or willing to relocate with an employer-provided relocation package (Preferred) Application Question(s): What is the maximum number of Team size handled? Which are your area of expertise with regard to MIS Tools? Work Location: In person

Job Summary We are looking for a motivated and energetic Account Manager to manage the TCL brand business in Kottayam . The ideal candidate should have at least 1 year of experience in field sales , preferably in the TV industry , and be capable of building strong B2B relationships and achieving regional sales targets. Key Responsibilities Handle B2B sales for TCL TV in the Kottayam region. Develop and maintain strong relationships with channel partners, dealers, and retailers. Achieve monthly sales and collection targets. Monitor stock movement, billing, and product visibility at retail counters. Visit dealers regularly, support secondary sales, and resolve trade issues. Conduct local market research and competitor analysis. Coordinate with the internal logistics and sales teams for smooth operations. Provide regular sales updates and market feedback to the reporting manager. Candidate Requirements Minimum 1 year of experience in field sales, preferably in TVs or electronics. Strong communication and negotiation skills. Knowledge of dealer/channel management. Willing to travel locally within Kottayam. Proficiency in MS Office (Excel, Word). Graduation in any discipline (MBA preferred but not mandatory). What We Offer Opportunity to work with a leading electronics distribution company. Competitive fixed salary + performance-based incentives. Travel and mobile allowance. Career growth within a professional and structured organization. Training and product knowledge support. About Company : Alps Distribution is Apple products authorised distribution company in Kerala and Tamil Nadu, headquartered in Cochin and have branches in Trivandrum, Thrissur and Calicut.Aldous Glare Tech & Energy (AGTE) is a sub company of ALPS.Aldous Glare, India’s leading distributor for Smartphone, Android TV, Google TV, Smart AC, Smart Washing Machine. For 30 years now, Aldous Glare Tech & Energy have stood the test of time and established ourselves as a brand synonymous with trust and quality. Technology and its advancements are ubiquitous and we function with the prime goal of increasing accessibility, awareness of the latest tech gadgets and appliances. We creates opportunities for its channel partners through aggressive market development and continuous improvements through agility. Company Website : www.aldousglare.com & www.alpsd.com Job Type: Full-time Pay: ₹25,000.00 - ₹28,000.00 per month Benefits: Cell phone reimbursement Flexible schedule Health insurance Internet reimbursement Leave encashment Provident Fund Schedule: Day shift Fixed shift Morning shift Supplemental Pay: Performance bonus Yearly bonus Work Location: Remote

Job Summary We are seeking a dynamic and driven Senior Account Manager to handle the TCL brand B2B business in Kollam & Trivandrum regions. The ideal candidate must have at least 1 year of experience in B2B sales , preferably in the consumer electronics/mobile/TV industry , and should be capable of independently managing dealer networks and driving regional growth. Key Responsibilities Develop and manage a strong dealer and distributor network for TCL products in Kollam & Trivandrum. Drive B2B sales of TCL TVs and other smart products by onboarding and activating new channel partners. Achieve monthly and quarterly sales and collection targets. Build strong relationships with channel partners to drive loyalty and business growth. Conduct regular market visits, dealer meetings, and promotional activities. Monitor competitor activities and provide actionable insights. Ensure timely billing, dispatch coordination, and payment collection. Maintain accurate reporting on sales, market conditions, and customer feedback. Candidate Requirements Minimum 1 year of experience in B2B sales (preferably in TV/mobile/electronics industry). Strong business acumen and negotiation skills. Proven ability to achieve targets and handle dealer accounts independently. Good communication and interpersonal skills. Proficiency in MS Office (Excel, Word, PowerPoint). Willing to travel extensively in Kollam and Trivandrum. What We Offer Work with a fast-growing national distributor of global technology brands. Competitive salary package with attractive incentives. Travel and communication allowances. Structured growth path and professional development. Energetic and collaborative work environment. About Company : Alps Distribution is Apple products authorised distribution company in Kerala and Tamil Nadu, headquartered in Cochin and have branches in Trivandrum, Thrissur and Calicut.Aldous Glare Tech & Energy (AGTE) is a sub company of ALPS.Aldous Glare, India’s leading distributor for Smartphone, Android TV, Google TV, Smart AC, Smart Washing Machine. For 30 years now, Aldous Glare Tech & Energy have stood the test of time and established ourselves as a brand synonymous with trust and quality. Technology and its advancements are ubiquitous and we function with the prime goal of increasing accessibility, awareness of the latest tech gadgets and appliances. We creates opportunities for its channel partners through aggressive market development and continuous improvements through agility. Company Website : www.aldousglare.com & www.alpsd.com Job Type: Full-time Pay: ₹27,000.00 - ₹30,000.00 per month Benefits: Cell phone reimbursement Flexible schedule Health insurance Internet reimbursement Leave encashment Provident Fund Schedule: Day shift Fixed shift Morning shift Supplemental Pay: Performance bonus Yearly bonus Work Location: Remote

The candidate will be part of the R&D in IP Group in India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design Verification using UVM based environment methodology. Job Description: The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP. Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with Perforce or similar revision control environment. Experience with Python/TCL or any scripting knowledge is an added advantage. Job Responsibilities Include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. Be single point of contact with hands-on experience on all verification tasks – Testbench Creation – Testplan creation – Coverage closure – SVA – Release Perform peer review of testbench code for continuous quality. Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. Lead team of engineers to perform various verification activities on IPs/Subsystems. Anticipate problems and risks and work towards a resolution and risk mitigation plan. Assist and mentor the team in day-to-day activities and grow the capabilities of verification team for future assignments. Review various results and reports to provide continuous feedback to the team and improve quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. The candidate must have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative. This position requires prior industry experience and is not open for college fresh grads. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. The Person A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Key Responsiblities Expertise in **power domain implementation** (UPF/CPF-based flow) for complex SoCs/IPs. Strong background in **power analysis** (static and dynamic), including IR drop, EM, and power grid validation. Hands-on experience with **low-power techniques** (multi-voltage, power gating, retention, etc.). Scripting skills (Python, Tcl, Perl) to automate power optimization workflows. Knowledge of **industry standards** and trends in power integrity, reliability, and energy efficiency. Why Join Us? Work on cutting-edge projects that redefine power-efficient design in semiconductors. Collaborate with a global team of innovators passionate about solving complex challenges. Grow your career with continuous learning, mentorship, and leadership opportunities. Competitive compensation, flexible work models, and a culture that values impact and creativity. Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated ASIC Digital Design Engineer with a passion for pushing the boundaries of technology. With a strong background in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI, you excel in functional verification flows and methodologies, particularly VMM, OVM/UVM, and System Verilog. Your expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation sets you apart. You possess fundamental knowledge of Analog and Digital mixed signal design, and your scripting skills in TCL/Perl/Python are top-notch. You are a team player with excellent communication skills, problem-solving abilities, and interpersonal skills, eager to deliver high-quality RTL and Simulation models to customers and support them through silicon bring-up and debug processes. What You’ll Be Doing: Develop and review the verification test-plan for multi-protocol 112G PHY IP (Serdes). Create and optimize the verification environment based on UVM. Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code). Deliver high-quality RTL and Simulation models to customers. Coordinate between RTL, Analog design, and Tech pub teams. Support customers with the integration and bring-up of IP in their simulation environments. Develop and deliver SV verification components for customer integration. Assist customers with silicon bring-up and debug issues when customer silicon is available. The Impact You Will Have: Ensure the delivery of robust and high-quality verification solutions for Synopsys’ high-performance PHY IPs. Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies. Enhance customer satisfaction through exceptional support and high-quality deliverables. Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches. Contribute to the development of industry-leading verification methodologies and best practices. Help maintain Synopsys’ reputation as a leader in chip design and verification solutions. What You’ll Need: B.Tech/M.Tech with 7+ years of relevant experience. Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog. Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation. Fundamental knowledge of Analog and Digital mixed signal design. Proficiency in scripting and automation using TCL/Perl/Python. Excellent debug and diagnostic skills. Who You Are: You are an innovative and detail-oriented professional with a strong technical background and a collaborative mindset. Your excellent communication skills, problem-solving abilities, and interpersonal skills make you a valuable team player. You thrive in a dynamic environment, continually seeking to improve processes and deliver high-quality results. Your passion for technology and dedication to customer success drive you to excel in your role. The Team You’ll Be A Part Of: You will join a dynamic and collaborative team focused on the verification of high-performance multi-protocol PHY IPs. Our team is dedicated to delivering innovative solutions and exceptional support to our customers, ensuring the successful integration and deployment of Synopsys IPs. Together, we drive technological advancements and set industry standards in chip design and verification. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

JOB NAME: - AMS Verification Engineer (Mandatory to have AMS verification with UVM test batch) BUDGET: - As per market standards LOCATION: - Hyderabad Please Note:it will be virtual interview, WFO initially later depends on the project and project manager, General shift. Job Description The position involves design verification of next generation IPs /SoCs with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate will require close interactions with Design, SoC , Validation, Synthesis PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. Responsibilities To work in AMS Verification domain with UVM test batch relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected Experience working on AMS Verification on multiple SOCs or sub-systems Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites Developing and validating high-performance behavior models Verifying of block-level and chip-level functionality and performance Team player with good communication skills and previous experience in delivering solutions for a multi-national client Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. Ability to extract simulation results, capture in a document and present to the team for peer review Supporting silicon evaluation and comparing measurement results with simulations UVM and assertion knowledge would be an advantage Experience Level: 5-20 years in Industry(3+yrs relevant) Education Requirements: Bachelor or Masters degree in Electrical and/or Computer Engineering Minimum Qualifications Proficient in at least one of the following languages: Verilog, System Verilog, Verilog AMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Python. Preferred Qualifications Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Benefits Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support This job is provided by Shine.com

The position requires 2-6 years of experience with micro architecture design and system design using Verilog, SV, or VHDL. You should also have experience in Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. Familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C is essential. You will be responsible for synthesis, timing analysis using various industry standard tools, and should have proficiency in TCL and Python scripting. The ideal candidate for this role should have a notice period of immediate availability to 1 month. The position is based in BLR/Hyd locations.,

You are an experienced Design for Testability (DFT) Engineer who will be responsible for leading and defining the overall DFT strategy for critical ASIC and SoC projects at HCL Tech. Your expertise in DFT methodologies is crucial for driving the implementation of robust test strategies to ensure the manufacturability and high-quality testing of next-generation integrated circuits. In this senior-level role, you will collaborate with design and verification teams to seamlessly integrate DFT techniques throughout the design flow. Your responsibilities include developing and implementing advanced DFT methodologies such as scan insertion, ATPG, Boundary Scan, and Design for X to achieve exceptional test coverage and fault detection rates. You will also champion best practices for DFT, participate in design reviews, mentor junior engineers, and analyze test results to identify and address potential design issues. To qualify for this position, you should hold a Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with a minimum of 10+ years of experience in DFT for complex ASICs and SoCs. Your proven track record of successfully leading DFT strategies for high-volume production and in-depth knowledge of advanced DFT concepts are essential. Additionally, expertise in industry-standard DFT tools and scripting languages for automation, as well as a strong understanding of digital design principles and manufacturing test processes, will be beneficial. Joining HCL Tech as a DFT Engineer offers competitive salary and benefits, the opportunity to lead cutting-edge DFT strategies, a dynamic work environment with professional growth opportunities, and recognition for outstanding contributions. If you are a highly accomplished DFT Engineer looking to make a significant impact in the field of integrated circuits, this role is perfect for you.,

We are seeking a talented and driven Senior QA Engineer to join our team at Pune, India. As a Senior QA Engineer, you will play a pivotal role in testing Platform products for wireless telecom and cloud-based cellular solutions at Parallel Wireless. You will collaborate with test engineers across different sites and have the opportunity to contribute to ORAN wireless technology. Your responsibilities will include: - Reviewing 3GPP standards, architecture, and design documents to develop comprehensive test plans for 5G NR/LTE testing. - Designing test plans for PHY/ Stack algorithms and considering end-to-end perspectives. - Generating test scripts using available tools and exploring innovative ways to replicate real-world scenarios. - Setting up simple or complex test environments as per test case requirements. - Developing test plans for LTE/5G NR features in compliance with 3GPP and ORAN standards. - Executing test cases, validating test outcomes, and interpreting log data for issue debugging. - Identifying system improvements based on test expertise and debugging field log/data. - Devising strategies for enhancing QA test planning and implementation efficiency. - Quickly diagnosing and resolving customer issues by replicating configurations in a lab environment. - Proficiency in K8S deployment and adapting deployment models across different platforms. Key qualifications: - 4-8 years of experience in various protocols for interoperability, performance evaluation, and troubleshooting radio access technology. - Strong background in RAN (5G/LTE) testing, feature testing, and lab testing. - Understanding of message flows and parameters in LTE/5G NR procedures. - Proficiency in scripting languages such as Python and Tcl. - Experience in creating complex test plans for 5G/4G features and root cause analysis. - Prioritization of automation and scripting skills for this role. Education requirements: - Bachelor's (B.E/B.Tech) or Master's degree (M.E. or M.Tech) in Electronics/Communication/Computer Science Engineering or equivalent field. Kindly note that the salary for this position is 0 - 0 per year.,

Tenstorrent is at the forefront of AI technology, setting new standards in performance, usability, and cost efficiency. With the evolution of AI reshaping computing, there is a growing need for innovative solutions that integrate advancements in software models, compilers, platforms, networking, and semiconductors. Our team comprises diverse technologists who have created a high-performance RISC-V CPU and share a common passion for AI, striving to develop the ultimate AI platform. We value collaboration, curiosity, and a dedication to solving complex problems. As we expand our team, we are seeking individuals at all levels to contribute to our mission. We are currently seeking an experienced engineer to lead the clock design efforts for our IP, CPU, and SoC teams. In this role, you will be responsible for defining clocking strategies that strike a balance between stringent timing requirements, power efficiency, and area constraints. You will collaborate closely with RTL, PD, and power engineers to construct robust, high-performance systems. This position is based in Bangalore and requires onsite presence. We invite candidates with a minimum of 6 years of experience to apply for this role. Throughout the interview process, candidates will be evaluated for their proficiency, and job offers will be made based on the assessment, which may vary from the details provided in this listing. As an ideal candidate: - You possess a solid background in clock tree synthesis and clock network design. - You are adept at working with timing, CDC, and low-power design methodologies. - You have experience working with advanced technology nodes, particularly 5nm or below, influencing design decisions. - You enjoy developing scripts to automate tasks and streamline engineering workflows. Key responsibilities include: - Taking charge of the end-to-end clock architecture for intricate SoCs. - Collaborating effectively with RTL, physical design, and power teams to achieve project objectives. - Proficiency in utilizing tools like Synopsys FC, ICC2, and scripting languages such as Python, Perl, or Tcl. - Demonstrating a problem-solving mindset focused on enhancing efficiency and resilience. This role offers the opportunity to: - Architect clocking strategies that are scalable across IP, CPU, and SoC designs. - Learn techniques to minimize power consumption and jitter while meeting aggressive power, performance, and area (PPA) targets. - Enhance workflows and reduce manual interventions through intelligent automation. - Address and resolve challenges specific to cutting-edge technology nodes. Join us at Tenstorrent and be part of a dynamic team dedicated to pushing the boundaries of AI technology.,

You are an experienced and highly skilled Senior SOC Design Verification Engineer with over 10 years of experience, specializing in PCIE (Peripheral Component Interconnect Express) protocols. As a key member of the team at Eximietas Design, you will be responsible for ensuring the robustness and correctness of cutting-edge System on Chip (SoC) designs. Your role will involve developing and implementing verification plans for complex SoC designs, with a particular focus on PCIE subsystems. You will work on creating and maintaining advanced testbenches using SystemVerilog and UVM (Universal Verification Methodology), as well as writing and executing test cases to verify functional and performance requirements, especially for PCIE protocols. Your responsibilities will also include debugging and resolving functional and performance issues in collaboration with design and architecture teams, developing and enhancing verification environments for PCIE and related interfaces, performing coverage-driven verification, and ensuring coverage closure. You will collaborate with cross-functional teams to define verification strategies and methodologies, mentor junior engineers, and contribute to the continuous improvement of verification processes. To qualify for this role, you should have a strong background in SoC design verification, with expertise in SystemVerilog, UVM, and PCIE specifications (e.g., PCIE Gen3/Gen4/Gen5) and verification methodologies. You should be proficient in developing and debugging complex testbenches and test cases for PCIE subsystems, with experience in coverage-driven verification and achieving coverage closure. Familiarity with AMBA protocols (AXI, AHB, APB), low-power verification techniques, power-aware simulation, and formal verification tools and methodologies will be beneficial. Strong problem-solving skills, attention to detail, excellent communication, and teamwork skills are essential for this role. Preferred skills for this position include knowledge of scripting languages like Python, Perl, or Tcl, familiarity with machine learning accelerators or AI/ML-based SoC designs, and experience with advanced process nodes (e.g., 7nm, 5nm). In return, Eximietas Design offers you the opportunity to work on cutting-edge SoC designs and innovative technologies in a collaborative and inclusive work environment. You will receive a competitive compensation and benefits package, along with professional growth and development opportunities.,

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collaborate with multi-functional teams to develop innovative DFT IP and play a crucial role in integrating testability features in the RTL. Working closely with design and PD teams, you will ensure the seamless integration and validation of test logic throughout all phases of implementation and post-silicon validation flows. Your team will contribute to the creation of innovative Hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die. You will drive re-usable test and debug strategies while showcasing your ability to craft solutions and debug with minimal mentorship. To excel in this role, you are required to have a Bachelor's or Master's Degree in Electrical or Computer Engineering along with a minimum of 10 years of relevant experience. Your expertise should encompass knowledge of the latest trends in DFT, test, and silicon engineering. Proficiency in Jtag protocols, Scan and BIST architectures, ATPG, EDA tools, and verification skills like System Verilog Logic Equivalency checking will be essential. Preferred qualifications include experience in Verilog design, DFT CAD development, Test Static Timing Analysis, and Post-silicon validation using DFT patterns. Your background in developing custom DFT logic and IP integration, familiarity with functional verification, and scripting skills like Tcl, Python, or Perl will be advantageous. At Cisco, we value diversity, innovation, and collaboration. We empower our employees to bring their unique talents to work, driving positive change and powering an inclusive future for all. As a company that embraces digital transformation, we encourage creativity, innovation, and a culture that supports learning and growth. Join us at Cisco, where every individual is valued for their contributions, and together, we make a difference in the world of technology and networking.,

As an intern in the SOC design team at MIPS, you will have the opportunity to be part of a 6-month or 1-year program. Candidates who have graduated in 2026 or later are eligible to apply, with 2025 graduates not meeting the qualification criteria. To be considered for this internship, you should possess a Master's or Bachelor's degree in Electronics Engineering, Electronics and Telecommunication Engineering, Computer Science, or Electrical Engineering. A strong academic track record with a CGPA of 8.0 or higher is preferred. The internship positions are available in Pune and Bangalore. Your main responsibilities will include designing and integrating subsystems into SoCs and contributing to the definition of RTL development flows for MIPS RISC-V processors. The key skills required for this role include proficiency in Verilog, SystemVerilog, VCS, Verdi, as well as strong scripting abilities in languages such as Tcl, Python, and Perl. Additionally, strong debugging skills will be beneficial in carrying out your day-to-day tasks effectively.,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design.: Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification Experience : 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT Experience : 1-3 Years.

Associate / Lead – Enovia CAD Integration Location: Chennai (Hybrid - 2-3 days WFO) Shift: Swing Shift (2 PM – 11 PM) Max CTC: ₹28 LPA 27376 Job Summary We are seeking a skilled Associate or Lead with 3-5 years of hands-on experience in developing and configuring solutions on the Enovia 3DExperience platform, with strong expertise in CAD integrations. The role involves participating in design workshops, analyzing business requirements, supporting system integration testing, reviewing technical designs, and driving Enovia PLM integrations such as CAD and SAP with modules like BOM and Change Management. Key Responsibilities Engage in design discussions and contribute technical insights to decision-making. Translate business requirements into IT requirements and review user stories for clarity. Execute system integration tests and validate data flows with PLM BOM and change management modules. Review technical designs and code for risk and alignment with business and IT needs. Develop test cases for functional feature validation. Champion Enovia PLM integration efforts (CAD, SAP) and ensure smooth interplay with existing modules. Collaborate with project managers and business stakeholders to provide timely updates. Required Experience & Skills 3-5 years of experience with Enovia 3DExperience platform development and configuration. Strong expertise in CAD integrations with systems like Creo/PDMLink, SolidWorks/EPDM, Inventor Vault, Solid Edge. In-depth knowledge of Enovia CAD integration technologies, including PowerBy and XPDM architectures. Proficiency with the 3DExperience data model (Classic and UPS) and UPS data model concepts. Familiarity with OOTB applications such as 3DPlay, Product Structure, 3D Visualization, 3D Issue & Markups. Experience in CAD data migrations is advantageous. Skilled in web-services based integration architecture. Programming experience with MQL scripts, TCL, JPOs, JSPs, and widget development on the 3DExperience platform. Strong SQL skills and familiarity with Oracle databases. Excellent communication, problem-solving, and analytical skills. Educational Qualifications Doctorate: 0 years relevant experience OR Master’s Degree: Minimum 3 years relevant experience OR Bachelor’s Degree: Minimum 5 years relevant experience Additional Details Only candidates with hands-on Enovia configuration and development experience will be considered. Pure installation/support experience is not sufficient. Target candidates from product-based or reputed service-based companies. Interview process: Three technical rounds + HR round. Skills: integration,mql scripts,ootb applications,tcl,cad data migrations,change management,3d,xpdm architectures,web-services based integration architecture,jsps,sql,analytical skills,jpos,oracle databases,cad,problem-solving,skills,plm,data,powerby,solid edge,business requirements,communication,solidworks/epdm,cad integrations,enovia 3dexperience,3dexperience data model,widget development,design,inventor vault,creo/pdmlink

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 12+ years of Hardware Engineering or related work experience. Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 10+ year of Hardware Engineering or related work experience. PhD in Computer Science, Electrical/Electronics Engineering, Engineering, with 8+ years of related work experience STA/Timing CAD Methodology Lead As an STA CAD methodology lead, the role would expect the candidate to lead deployment of new features and or methodologies related to STA and ECO domain Scope of the work would cover (but not limited to) STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few) There would be challenges for timing convergence at both block and Top level on cutting edge technology on high performance designs would have to be resolved for ensuring successful design tapeouts on time with high quality. Key requirements: Thorough knowledge of the ASIC design cycle and timing closure flow and methodology. 10 + years of proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow. Strong understanding of advanced STA concepts and challenges in advanced nodes Proficiency scripting languages (TCL, Perl, Python). Strong background in PNR and Extraction domain. Experience of constraints development tool (like spyglass) will be added advantage. Leadership qualities to lead (technically) and manage the STA CAD team Qualification: BE/BTech + 12 years of experience, or ME/MTech + 10 years of experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 12+ years of Hardware Engineering or related work experience. 3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF). 3+ years of experience utilizing schematic capture and circuit stimulation software. 3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry. Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues. Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Qualcomm CDMA Technologies (QCT) is a global leader in Multimedia integrated circuits (ICs), software and systems for wireless consumer devices including Smartphones, Netbooks and E-readers. Our teams are developing advanced technologies to enhance mobile devices in areas including 2D and 3D graphics, audio/video, display and architecture. These Multimedia ASICS are co-designed with our Modems, Applications Processors, Analog Codecs and Power Management ICs to deliver highly-integrated, high-performance and low-cost chipsets to our customers and partners. You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume productionExperience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT)Experience with Computer Architecture, Computer Arithmetic, C/C++ programming languages is desiredExposure to DX9~12 level graphics HW development is big plusGood communication skill and desire to work as a team player RequiredBachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field.PreferredMaster's degree in Computer Science, Electrical Engineering, Information Systems, or related field. ASIC, hardware, design, GPU, OpenGL, DirectX, RTL, Verilog, SystemVerilog Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Description TCL Cables Limited has been a leading manufacturer of control cables, thermocouple cables, and instrumentation cables since 1980. Based in Delhi, the company is known for its quality products that serve various industrial applications. TCL Cables Limited is committed to innovation, quality, and customer satisfaction. Role Description This is a full-time on-site role based in Hyderabad for a Senior Technician. The Senior Technician will be responsible for maintaining and repairing cable machinery, ensuring the quality of produced cables, troubleshooting technical issues, and collaborating with the engineering team for process improvements. Daily tasks include performing routine maintenance, executing technical tests, and adhering to safety protocols. Qualifications Technical skills in machinery maintenance and repair Experience with quality control and technical testing Ability to troubleshoot and solve technical issues Knowledge of safety protocols and procedures Strong analytical and problem-solving skills Ability to work collaboratively with cross-functional teams Bachelor's degree or equivalent in a relevant field is preferred

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Analog Layout. Experience: 1-3 Years. >

Legal & Compliance Services LOB Financial Services PREFERRED SECTOR/INDUSTRY Legal & Compliance DESIGNATION B2 Sr. Analyst QUALIFICATION CS. (Must) LL. B (preferred but not mandatory) JOB LOCATION Delhi/NCR EXPERIENCE REQUIRED 3.5- 6 years JOB RESPONSIBILITIES The role of Sr. Analyst in Legal & Compliance shall encompass various tasks including, but not limited to, the following: Preparation of management committee meetings, board meetings and the GPs of Client funds Drafting of management committee and board meetings minutes and review of GP minutes including maintaining policies/minutes trackers/action logs in this respect Manage corporate and legal & compliance process Ensure quality assurance and checking for all the deliverables Ensure creation of training plans and manuals, quality manuals, SOPs, query log, escalation matrix, guidelines, checklist, etc. Manage team and accountable for QAs/QCs/Analyst work Oversee Implementation of the Quality system in the project Quickly and effectively train resources on process and client tools. Creating SOPs, guidelines, checklist, quality manuals, training manuals etc. Reports to Team lead DESIRED SKILLS & COMPETENCIE Candidate should have at least 3.5 6 yearsexperience in the legal/corporate department of a fiduciary or have worked in a law firm. Candidate should be willing and looking to consolidate and grow the skills and talents in the long term with a company that works in a dedicated team and results-based environment. Technical Skills Knowledge of regulatory and corporate environment for Irish/Luxembourg funds Understand key challenges General Counsels face in running corporate legal departments and functioning of law firms Engage with Clients, support decision making, delivery/governance related discussions Skills in planning, evaluation, research, analysis, training, problem solving and reporting Ability to facilitate and contribute to client sessions to define, illustrate and gain buy in to substantial departmental transformation via legal services Ability to perform email outreach to client Expert in analyzing legal and compliance issues Functional Skills Excellent written and oral communication in English Proficiency in using MS office Suite Experience in managing multiple/large teams Experience in Delivery and related governance Handling Client Escalations, Resourcing, People Management, Project Deliverables Implementing the Quality system in the project Ensuring appropriate use of methods, tools, and techniques in project Co-ordinating customer-related activities including acceptance of the deliverables Engage with Clients, support decision making, delivery/governance related discussions

Meet the Team Data Center Networking Group develops the Nexus 9000 line of data center and cloud switches that feature application awareness to make the network infrastructure flexible and agile for dynamic response to application needs and virtual machine workload mobility. Data Center also developed a 400G, 800G Ethernet transceiver crafted to drastically lower the optics price to out challenge the competitor offerings. As we realize our modernization strategies and move into new markets, our diverse, inclusive culture also creates a competitive advantage for Cisco. It ensures we have the fresh ideas and execution capabilities and the local knowledge to best serve our customers and build Cisco brand recognition around the globe. By gaining a better understanding of the world and the differences in its people we can change the way it works, lives, plays, and learns. Your Impact In depth understanding of hardware boards, layout Development experience in one or more areas of BIOS/GRUB/uboot, linux device drivers/ Linux KLM, networking stack, memory model Development experience on PCH and peripherals PCI, I2C, SPI, Higig+ bus, FPGA and CPLD handling, handling os special devices and peripherals – I2C-GPIO expanders. Exposure to standards – XAUI, SGMI, Serdes, SGMII, MSA Development experience in Chassis management Knowledge of asic forwarding, Linux drivers and 3rdparty ASICs/network processors highly desired. Excellent debugging skills and rich experience using various hardware, memory debugging tools Minimum Qualifications: B.E/B.Tech/ME/Mtech/MS from reputed university and at least 8-12 years of software development experience in embedded systems or system software space Hands on Engineer/leader who can work along with senior folks contributing to Architecture, design and development of platform development cycle Develop innovative solutions to redefine for the next generation data center. Preferred Qualifications: Familiar with Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Working experience in merchant silicon Ability to multi-task and solve complex problem Knowledge of asic forwarding, Linux drivers and 3rdparty ASICs/network processors highly desired. Consistent track record of learning new technologies and features on own initiative A demonstrable passion for technology and software development #WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!