Radiant Semiconductors is a leading Semiconductor Design and Services Company with a strong presence across India and the USA. Backed by 200+ skilled engineers, over 7 years of industry relevant experience, were specialised in Design Verification, Design For Test (DFT), PD and Analog Design. We deliver tailored solutions through flexible engagement models, serving top Semiconductor Companies worldwide by our leadership team with 18+ years of expertise in product development. Role: Junior DFT Engineer Location : Bengaluru, Candidate should be flexible to work PAN India Eligibility Criteria Qualification : B.E/ B.Tech, M.Tech/M.E (Will get preference) Stream : Electronics Engineering or Related Fields Post Graduation Year : 2024 or Prior (Up to 2020) Academic Requirement : Minimum 65% throughout academics Background : Strong foundation in VLSI Design, Digital Electronics, Scan & DFT Fundamentals What we offer Competitive Salary Package aligned with Industry Standards Comprehensive Family Health Insurance Coverage Opportunity to work on high-impact semiconductor projects with top-tier global clients Professional training with the focus on industry standard EDA tools Opportunity to continuous learning and mentorship support from Industry experts Employee Recognition: Get acknowledged and rewarded for innovation, performance, and dedication Selection Process Online Registration Written Test (Shortlisted Candidates) Technical Interview (Selected Candidates) HR Discussion & Final Offer Important Dates Last Date to Application- 14th June Written test (Shortlisted Candidate )- 27th June Technical Interview (Selected Candidates)- 28th June HR Discussion & Final Offer- 28th June Click on the link to Apply now and become a part of Radiants Dynamic DFT team: https://forms.gle/ZCNcACE9Eigx5iuq6

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Details: : Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 7+ years of DFT experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

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At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a safer, sustainable and more connected world. Job Overview TE Connectivity's Manufacturing Engineering Teams are process leaders for stamping, molding or assembly related topics, ensuring the processes are running at optimum levels for quality and output. They are experts in mold tooling, die tooling, machining, and assembly techniques, possessing extensive knowledge of the associated manufacturing processes which may include the optimization and standardization of stamping / molding / assembly or other processes within the manufacturing environment. Manufacturing Engineering Teams enable the TE business unit plants to reach TE Operating Advantage (TEOA) requirements, roll out Centers of Excellence (COE), Best Demonstrated Practices (BDP s) and advise plants on tool and machine duplications / corrections / improvements. They design and develop manufacturing process and automation platforms and apply them for the realization of new product developments as well as optimization of existing products already in production. The Teams also support Product Development in the selection and optimization of tools for piece part production and the selection of the most suitable manufacturing concepts relative to planned manufacturing quantities, quality requirements and manufacturing location. They act as interface between engineering and production to ensure manufacturability of new designs and smooth production ramp up as well as support the research & development teams to produce sample manufacturing equipment, product samples and prototypes. Responsibility: Analyze new technology and manufacturing processes. Plan and assess the feasibility of new and running projects. Hands on experience in new product development, costing , establish components with optimized CT. Responsible for programming turn, mill, mill-turn, multi-axis machine and process. Product estimation & product costing for machined components, subcon activities, standard parts & assembly process, make vs buy analysis as per scope of supply. Implementing digital factory, cloud-based systems, AI Vision, AR/VR, IOT, Industry 4.0, Machine connectivity, Traceability Systems through wi-fi as well as wired network. Vendor management, Installation, and commissioning of new Equipment s and co-ordinate with Vendor/CFT for complete process validation. Establish tooling, gauge & review fixture designs, CPC calculation and proving out FAI parts and coordinating with shopfloor for mass production. Develop new process , tooling s and create all process documents like PFC, PFMEA, Control plan and SOP by understanding the depth of product requirements Prepare CT & Investment for new product and always work on to reduce cost by optimization/automating process to reduce cost. Responsible for ordering spares and vendor management, down time reduction Capacity & Layout planning/execution for new product line. Support manufacturing for Continuous Improvement, quality issues on the floor, new launches, engineering changes and Lessons Learnt. Develop and implement systems that optimize all phases of production process. Conduct Root-Cause Analysis. Review designs for manufacturing feasibility, suggest changes to the design to ensure product cost effectiveness Establish Tool management System (TMS), Calibration management, Document management Systems like Vicidocs, IQ-RM, Etc. Implement Process monitoring and Control (SPC & SQC), quality traceability Systems using IOT technology. Hands on experience on mechanical 3D design software s like CAD/CAM , NX CAM, NX CAD, Solid CAM, Vericut, SAP MM, TCL & C Language (Basic Desired Candidate Profile EDUCATIONAL/CRITICAL EXPERIENCE B.E./B. Tech in Electrical, Electronics, Mechanical, Mechatronics, or similar technical field. MBA in Marketing would be an added advantage KEY COMPETENCIES Strong analytical thinking and eagerness to learn about product development and market dynamics. Effective communication and collaboration skills across technical and non-technical teams. Basic knowledge or exposure to CAD tools, technical drawings, or electrical/mechanical components are a plus. Familiarity with Excel, PowerPoint, and willingness to learn tools like Power BI or Salesforce. Passionate about making a real-world impact through innovative product design and business alignment. Knowledge of basic electrical and electronics circuits, statistical analysis tools and data analysis Competencies EOE, Including Disability/Vets Location

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities Digital design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools PPA characterization and optimization of these performance-oriented and power-oriented best-in-class IP cores for advanced process nodes, such as 7nm/5nm/3nm/2nm Development, automation and maintenance of EDA flows and scripts for physical implementation Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs Participate in benchmarking PPAs for customer engagements Required Skills – Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes 3+ years of relevant experience in ASIC design environment Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification Experience with Cadence digital design tools will be an added advantage Hands on scripting languages like Python, Perl, TCL, Unix shell etc Strong understanding of digital logic design, processor design, and computer architecture is desirable Should have excellent communication, analytical and problem solving skills Should be self-motivated and good team player We’re doing work that matters. Help us solve what others can’t. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world’s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system‐level knowledge, Marvell's infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments. What You Can Expect Lead DV efforts for blocks, subsystems, and top-level verification. Develop and maintain UVM-based verification environments. Define and review test plans with architecture and design teams. Verify designs using directed and constrained random techniques. Maintain regression, debug failures, and analyze coverage. Drive verification to meet coverage targets. Contribute to next-gen data processing and hardware accelerator verification. Focus on networking domain verification for future solutions. Ensure design closure using innovative and automated techniques. What We're Looking For Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field with 8+ years of professional experience. Strong experience with Verilog, SystemVerilog, and UVM. Expertise in unit and subsystem verification, modern verification concepts. Proficiency in SystemVerilog, C, C++, and scripting (Perl, Tcl, Python preferred). Strong debugging skills and verification flow optimization. Collaborate with design teams on specs, test plans, and verification strategies. Develop and maintain UVM-based testbenches for ASIC SoCs. Execute verification, maintain regressions, and debug failures. Excellent verbal and written communication skills. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Description As a Electrical Validation Engineer, you will be part of Validation team that is exploring new hardware designs to improve our devices. In this role, you will create, define and develop electrical validation environment and test suites. You will also be responsible for the development of methodologies, execution of validation plans, debug of failures and follow up to closure. Key job responsibilities Role You will work closely with multi-disciplinary groups including Board Design, System Architects, IP developers, and Software Engineering, to verify and deliver complex, high volume SoCs that enable development of world-class hardware devices. In this role, you will: Perform electrical compliance test specifications / compliance test suite for various interfaces and conduct lab measurements Work on high-speed serial I/O interfaces like (LP)DDR4/5, USB, CSI/DSI, HDMI, PCIe interfaces etc. Perform documentation and communicate data across large number of tests and measurement results Drive initiatives to improve process, procedures, and quality of High Speed Characterization at SOC & Product level. Work on schematic and PCB physical design tools to interpret the design and locate physical probe points. Basic Qualifications Bachelor’s degree or higher in EE, ECE, or CS High speed serial interface analog building blocks, protocol, specifications and test methods Writing Python/TCL/PERL code to automate test procedures Good software architecture principles and development practices PCB layout best practices Preferred Qualifications MS/ME in Computer Science, Electrical Engineering, or related field Proficiency in handling High Bandwidth oscilloscopes, BERT, logic analyzers and understanding of probing techniques Understanding of Power & signal integrity concepts such as differential impedance, jitter, insertion loss, return loss, termination, etc. Scripting experience in any programming language (C++, Python, PERL, MATLAB) to develop automation scripts is a plus. Experience in Analog IP Characterization (SerDes, PLL, DDR) is desirable. Familiarity with Transmitter and Receiver design blocks. Understanding of equalization techniques (CTLE/DFE). Good understanding of High-Speed Analog/Digital Circuits, VLSI, semiconductor physics Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Company - ADCI - BLR 14 SEZ Job ID: A2866703 Show more Show less

Role & responsibilities Expertise with FPGA debug and HW testing - Using ChipScope Expertise with Board debug using Oscilloscope, Power supplies Ability to read and understand PCB Schematics, layout files RTL Coding in Verilog, System Verilog or VHDL Strong understanding of FPGA flow, Logic design, Digital design etc. Knowledge in Xilinx FPGA architecture Good Knowledge in Tcl, Python scripting Preferred candidate profile Ability to communicate technical information in an organized and understandable fashion. • Customer oriented approach with a demonstrated concern and desire to work with and assist customers. • Good organizational skills with the ability to multitask, prioritize, and track many activities. • Outstanding oral and written communication skills.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience required 8+ Years. Emulation experience on any available platforms (Palladium, Veloce or Zebu) including bring-up, VIP interfacing, build flow, debug, performance/throughput measurement Good understanding of the SOC designs and verification aspects Experience with Verilog, System Verilog, UVM, SVA Knowledge of communication/interface protocols would be a plus: PCIe, USB3/4, LPDDR5/4 , QUP, eMMC, SD, UFS Knowledge of the processor RISCV, ARM Knowledge of GLS and GLE flows would be a plus Proficient in writing scripts using any languages (Perl, TCL, bash, Python) Experience with waveform debug tools like Verdi Strong communication skills and ability to work as a team with multiple stakeholders Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073184 Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 12+ years of Hardware Engineering or related work experience. Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 10+ year of Hardware Engineering or related work experience. PhD in Computer Science, Electrical/Electronics Engineering, Engineering, with 8+ years of related work experience STA/Timing CAD Methodology Lead As an STA CAD methodology lead, the role would expect the candidate to lead deployment of new features and or methodologies related to STA and ECO domain Scope of the work would cover (but not limited to) STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few) There would be challenges for timing convergence at both block and Top level on cutting edge technology on high performance designs would have to be resolved for ensuring successful design tapeouts on time with high quality. Key Requirements Thorough knowledge of the ASIC design cycle and timing closure flow and methodology. 10 + years of proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow. Strong understanding of advanced STA concepts and challenges in advanced nodes Proficiency scripting languages (TCL, Perl, Python). Strong background in PNR and Extraction domain. Experience of constraints development tool (like spyglass) will be added advantage. Leadership qualities to lead (technically) and manage the STA CAD team Qualification BE/BTech + 12 years of experience, or ME/MTech + 10 years of experience Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Preferred Qualifications Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 12+ years of Hardware Engineering or related work experience. 3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF). 3+ years of experience utilizing schematic capture and circuit stimulation software. 3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties And Responsibilities Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry. Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues. Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers. Level Of Responsibility Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3065939 Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073060 Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. PVT Sensor IP development is a critical offering for process, voltage, temperature and other monitoring IPs within SOC subsystems. Synopsys is a market leader for these IP developments which are integral parts of Silicon lifecycle monitoring. You Are: As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules. Contribute to the development and enhancement of layout design methodologies and best practices. Work closely with different function design leaders to understand/enhance processes and help to enhance methodology. Collaborate with internal infrastructure teams on compute grid, storage management, and job scheduling architecture, efficiency, maintenance, and forecasting. Understanding CAD infrastructure and methodology will help to set up project environments. Contribute to enhancing quality assurance methodology by adding more quality checks/gatings. Front End development process understanding and support internal tools development and automation to help improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Stay updated with the latest industry trends and advancements in A&MS layout design. Understanding of tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views will add value to this position. Writing RTL Code and TCL is a good addition. The Impact You Will Have: Enhance layout design methodologies and best practices, contributing to the overall quality and efficiency of the design process. Improve project forecasting capabilities by leveraging advanced monitoring and scheduling techniques. Boost productivity across ASIC design cycles through the development and automation of internal tools. Ensure design integrity and manufacturability through meticulous physical verification and design rule checks. Stay at the forefront of industry advancements, bringing the latest trends and technologies into Synopsys' design practices. Collaborate effectively with cross-functional teams, driving innovation and continuous improvement in design methodologies. What You’ll Need: Bachelor’s or master’s degree in engineering or a related field. 2 to 3+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills. Who You Are: You are a highly motivated individual with a strong technical background and a passion for innovation. You possess excellent problem-solving skills and thrive in a collaborative, team-oriented environment. Your ability to adapt to fast-paced, dynamic work settings and your proactive approach to challenges make you an invaluable asset to the team. You are dedicated to continuous learning and staying updated with industry advancements, ensuring that your contributions drive Synopsys' success in the competitive semiconductor landscape. The Team You'll Be A Part Of: You will be joining a dynamic and forward-thinking team focused on developing cutting-edge PVT Sensor IPs and enhancing SOC subsystems. Our team is dedicated to pushing the boundaries of technology and innovation, ensuring that Synopsys remains a market leader in the semiconductor industry. Collaboration, continuous improvement, and a commitment to excellence are the core values that drive our team's success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process Show more Show less

We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities. Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes. The successful candidate: has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design. has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements Independent, timely decision maker and able to cope with interrupts Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools. Show more Show less

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Dassault Systemes ENOVIA V5 Good to have skills : No Function Specialty Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. You will oversee the development process and ensure successful implementation of applications. Roles & Responsibilities:1.Capable of understanding and contributing to the technical solution from 3DEXPERIENCE design through code level.2. Capable of providing solutions & mentoring support to the team.3.Taking ownership of individual tasks (implementation and bug fixing) and ensuring the delivery of assignments on-time with quality. Extending Support to the team when required4.Awareness and adherence to the best practices to the coding standards of Enovia API/EKL/CAA. Professional & Technical Skills:1. Must have skills- 3DExperience/CATIA/Enovia - Customization2. Experience with 3DExperience Enovia customization, configuration and SME role.3. Excellent verbal and written communication skills. Additional Information:1. The candidate should have a minimum of 4+ years of experience in 3DExperience/CATIA/Enovia - Customization.2. Should be a team player.3. This position is based at our Bengaluru office. Qualifications 15 years full time education

Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years What would you do? "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for? " Agility for quick learning Ability to work well in a team Process-orientation Written and verbal communication Network fundamentals Understanding all the networking devicesRouters, switches, etc. IP connectivity, access, addressing, and services Network security fundamentals Installation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business Networks Excellent Communication Problem Solving Skills Flexibility Teamwork Experience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: " In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shifts Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the output Manage client s optical network, manage alarms and faults in a multi-vendor environment, and Tracking of all work in ticketing system network interconnects with internal and external network operators Track and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providers Manage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary. Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacement Read/Parse vendor notifications and translate to Clients Production Change Request (PCR s) Look up affected circuits to include them in change request Escalate any emergency change requests for immediate review and scheduling Navigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation

Project Role : Sales Capture Practitioner Project Role Description : Shape, sell and close deals that are single or multi service. Shephard the deal to develop the win strategy, the negotiation strategy, and the close plan. Must have skills : Sales Pursuit Management Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Sales Capture Practitioner, you will shape, sell, and close deals that are single or multi-service. Shephard the deal to develop the win strategy, the negotiation strategy, and the close plan. Be involved in the entire deal lifecycle from start to finish, ensuring successful outcomes. Roles & Responsibilities: Expected to be an SME, collaborate, and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Expected to provide solutions to problems that apply across multiple teams. Lead the development of win strategies for deals. Create and execute negotiation strategies for successful deal closures. Manage and oversee the entire deal lifecycle. Provide guidance and mentorship to junior team members. Professional & Technical Skills: Must To Have Skills:Proficiency in Sales Pursuit Management. Strong understanding of sales methodologies and techniques. Experience in developing and executing sales strategies. Excellent communication and negotiation skills. Ability to analyze market trends and customer needs. Additional Information: The candidate should have a minimum of 12 years of experience in Sales Pursuit Management. This position is based at our Hyderabad office. A 15 years full-time education is required. Qualifications 15 years full time education

Blackbaud unleashes the potential of the people and organizations who change the world, and we’re growing our team. As the leading software provider exclusively dedicated to fueling social impact, you can expand what is possible across the nonprofit and education sectors and work with companies committed to social responsibility, so you can expand what is possible. As a Senior DevOps Engineer focused on Site Reliability within Infrastructure Engineering and Cloud Operations (IECO), you will contribute to the development of our solution delivery platforms supporting our web-based applications on the latest cloud technologies within a DevSecOps culture. You will have the opportunity to utilize automation technologies and private/public cloud technologies to provide world-class solutions that serve the non-profit industry. What you’ll do Build automation leveraging CI/CD processes, automated testing, unit testing, code coverage and other software development best practices Contribute to reusable automation scripts, libraries, services, and tools to increase system and process efficiencies Partnering with the security teams and tools to continually review and understand new industry security threats, associated technologies and quickly addressing vulnerabilities Pursue opportunities to further operational excellence by increasing efficiency and reducing risk, complexity, waste and cost Partner with key stakeholders to establish technical direction and negotiate technical decision points to drive innovative solutions Drive technical design and validation, while ensuring implementation aligns with our technical strategies and strategic business goals Develop architectural designs for applications building something to delight clients while managing costs to deliver these applications What we’ll want you to have: 5+ years of experience with common web technologies required – Javascript, C#, .NET, HTML, AJAX or other equivalent Object-Oriented language 5+ years of experience in the implementation of cloud technologies (Microsoft Azure) and an understanding of SAAS, PAAS, and IAAS models Experience building high performance, scalable, robust, 24x7 environments and/or applications Experience creating scripts or automation, such as Perl, PowerShell, Python, TCL/TK, Ruby or similar for cloud orchestration required (PowerShell preferred) Available on a 24x7x365 basis when needed for production impacting incidents or key customer events Ability to create quality code that is secure and operable at scale India Location Our India location is a cornerstone of our global efforts, where innovation and collaboration come together to drive our mission forward. This stems from our commitment to expanding our global impact by harnessing the incredible talent pool in Hyderabad. Here, you’ll find a supportive and inclusive environment that values your contributions and encourages growth, both professionally and personally. We offer a hybrid work model, blending remote and in-office work to allow flexibility while supporting you personally and professionally. We Thrive Together! Stay up to date on everything Blackbaud, follow us on Linkedin, X, Instagram, Facebook and YouTube Blackbaud is a digital-first company which embraces a flexible remote or hybrid work culture. Blackbaud supports hiring and career development for all roles from the location you are in today! Blackbaud is proud to be an equal opportunity employer and is committed to maintaining an inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, physical or mental disability, age, or veteran status or any other basis protected by federal, state, or local law.

About the role As a Staff DevOps Engineer focused on Site Reliability within Infrastructure Engineering and Cloud Operations (IECO), you will contribute to the development of our solution delivery platforms supporting our web-based applications on the latest cloud technologies within a Dev Sec Ops culture . You will have the opportunity to utilize automation technologies and private/public cloud technologies to provide world-class solutions that serve the non-profit industry. What you'll do Build automation leveraging CI/CD processes, automated testing, unit testing, code coverage and other software development best practices Contribute to reusable automation scripts, libraries, services, and tools to increase system and process efficiencies Partnering with the security teams and tools to continually review and understand new industry security threats, associated technologies and quickly addressing vulnerabilities Pursue opportunities to further operational excellence by increasing efficiency and reducing risk, complexity, waste and cost Partner with key stakeholders to establish technical direction and negotiate technical decision points to drive innovative solutions Drive technical design and validation, while ensuring implementation aligns with our technical strategies and strategic business goals Develop architectural designs for applications building something to delight clients while managing costs to deliver these applications What you’ll bring 2+ years of experience with common web technologies required – Javascript , C#, .NET, HTML, AJAX or other equivalent Object-Oriented language 2+ years of experience in the implementation of cloud technologies (Microsoft Azure) and an understanding of SAAS, PAAS, and IAAS models Experience building high performance, scalable, robust, 24x7 environments and/or applications Experience creating scripts or automation, such as Perl, PowerShell, Python, TCL/TK, Ruby or similar for cloud orchestration required (PowerShell preferred) Available on a 24x7x365 basis when needed for production impacting incidents or key customer events Ability to develop quality code that is secure and operable at scale Stay up to date on everything Blackbaud, follow us on Linkedin, X, Instagram, Facebook and YouTube Blackbaud is a digital-first company which embraces a flexible remote or hybrid work culture. Blackbaud supports hiring and career development for all roles from the location you are in today! Blackbaud is proud to be an equal opportunity employer and is committed to maintaining an inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, physical or mental disability, age, or veteran status or any other basis protected by federal, state, or local law.

Roles and Responsibilities: Work with offshore and global teams to understand project scope including analysis domain, boundary condition, material models, type of analysis etc. Active Coordinator for multiple groups that include Design, Aerodynamics and Structures teams for Project specific inputs Ability to work autonomously and prioritize multiple projects Review technical presentations, interpret the results and present the same to Customer Expertise in dealing with Design and Technical Discipline reviews Responsible for ensuring 100% quality and on-time delivery Conduct project review meetings to share the lessons learned and best practices to the team to improve the quality Responsible for providing alternative solutions on field issues Responsible for process improvements by developing Automation tools Work on complex CAE problems to assist product development Prepare Technical proposals and Business cases for new process improvement areas Perform Design Modifications as per need and validating the same with FEA Demonstrate Excellent Technical, Project Management, Interpersonal and Problem solving skills Mandatory skills: Minimum 6 years of experience in Stress analysis of Aero engine components (Rotors, Cases, Stators and Externals) using commercial Finite Element Analysis tool. Expertise in handling various structural analysis tools preferably ANSYS Classic, Ansys Workbench, Hypermesh etc 2D & 3D Finite Element modeling of simple, moderate and complex components (Hexahedral & tetrahedral elements) using ANSYS-APDL or Workbench Linear and non-linear static stress analysis (Geometric, Material and contact Linearity) using ANSYS-APDL or Workbench Modal, Harmonic and transient Dynamic stress analysis using ANSYS-APDL or Workbench Strength, stability and Durability of components Damage tolerance analysis to estimate fracture life Should able to develop/modify APDL Macros Should able to build/update FE Models in HyperMesh. Desired Skills: Experience in scripting using Matlab, VB,TCL/Tk, Python is an added advantage Knowledge of Hand Calculations, Standards and Design codes is an added advantage Basic Knowledge of CAD tools is and added advantage Roles and Responsibilities Execute Stress analysis projects of Aero engine components (Rotors, Cases, Stators and Externals) using ANSYS-APDL or Workbench independently.

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA