Perform
synthesis of complex SoCs
at both block and top levels.
Develop and write
timing constraints
for intricate designs, including those with multiple clocks and voltage domains.
Lead
post-layout timing closure
for multiple tape-outs, including handling timing ECOs and achieving STA signoff.
Develop
I/O constraints
for industry-standard protocols such as DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display, etc.
Conduct
formal verification
(RTL-to-netlist and netlist-to-netlist) with DFT constraints.

Skills

Expertise in
synthesis
and
Static Timing Analysis (STA)
.
Proficiency in writing
timing constraints
for complex designs.
Hands-on experience with
post-layout timing closure
, including timing ECOs.
Expertise in
I/O constraint development
for various industry-standard protocols.
Strong knowledge of
EDA tools
such as RC, DC, PT, PTSI.
Good understanding of
VLSI process and device characteristics
.
Good understanding of
deep submicron parasitic effects and crosstalk effects
.

Qualifications

B.Tech. or M.Tech. with relevant experience in Synthesis, STA.
Hands-on experience working on technology nodes like
28nm, 20nm, 14nm, 10nm

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