4 Technology Nodes Jobs

Looking for Siemens EDA ambassadors: Lead Software Engineer for Product Validation and Customer support for PowerPro If you are passionate about innovations that lead to real progress, and if you are curious about technologies that are yet to be developed, then this opportunity might be for you. Utilize your curiosity, passion, and creativity to enhance the lives of millions of people. Join us and share your unique perspective with us! As a valuable member of the Siemens EDA team, your role will involve contributing to the growth of efficiency and customer satisfaction within Siemens EDA's Power platform. This challenging position aims to support the expansion of Siemens's EDA business in India. You will be a part of the DDCP (Digital Design Creation Platform group), which encompasses renowned industry tools like Tessent, PowerPro, Catapult, and Aprisa. Operating within the DPRS (Devops, Product, Release & Support group) under DDCP, you will be focused on cutting-edge tools like PowerPro. Your responsibilities will revolve around Product Validation, Customer Support, and Release tasks for the PowerPro tool, a commercially available RTL sequential power optimization and power analysis tool. Join our energetic and passionate team driven by synergy and enthusiasm. **Key Responsibilities:** - Collaborate with the Product Validation and Customer Support team to validate and educate on the features of PowerPro. - Validate all features of the tool as an internal end-user, identify and report issues, develop test plans, write test cases, and enhance the product quality and test environment. - Assist in supporting and debugging customer test design methodologies using our products. - Engage in architecture reviews, contribute to defining feature prototypes, understand customer design flow requirements, and propose optimization measures. - Analyze customer-reported bugs, enhance testing procedures, incorporate new designs/flows, respond to customer inquiries using technical expertise, demonstrate products, and provide field application support to customers. - Lead and mentor 1-2 junior team members or interns, guiding them in their day-to-day activities. **Qualifications:** - B.Tech in Electrical/Electronics & Communication Engineering or M.Tech in VLSI/Microelectronics with 3+ years of relevant industry experience. - Profound knowledge of ASIC design flows, digital logic, and RTL/gate-level simulation and verification methodologies. - Proficiency in Verilog, VHDL, and SystemVerilog (SV). - Demonstrated understanding of low-power SoC design concepts, including power intent (UPF) and power-aware design methodologies. - Experience with simulation, synthesis, place & route tools and flows. - Hands-on expertise with industry-standard tools such as Power Artist, Joules, Prime Power/PTPX, Questa, VCLP, and Design Compiler (DC). - Proficiency in scripting languages like Perl and Tcl, with knowledge of Python being advantageous. - Strong problem-solving, debugging skills, and familiarity with RTL/gate-level simulation, emulation, SPEF, and various technology nodes. - Experience in EDA CAD support for RTL design teams is a plus. - Excellent communication skills, adaptable, collaborative, self-driven, and experienced in team leadership. Siemens is a global organization with over 377,000 individuals shaping the future in more than 200 countries. We are committed to equality and welcome applications that represent the diversity of the communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business needs. If you bring curiosity, creativity, and the drive to shape tomorrow, we invite you to join us on this journey. Transform the everyday. Accelerate transformation. Hybrid.,

This role is for an STA Engineer to be a key contributor in the synthesis and static timing analysis of complex SoCs. The ideal candidate will have extensive experience in timing closure, I/O constraint development for industry-standard protocols, and hands-on experience with advanced technology nodes. Responsibilities Perform synthesis of complex SoCs at both block and top levels. Develop and write timing constraints for intricate designs, including those with multiple clocks and voltage domains. Lead post-layout timing closure for multiple tape-outs, including handling timing ECOs and achieving STA signoff. Develop I/O constraints for industry-standard protocols such as DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display, etc. Conduct formal verification (RTL-to-netlist and netlist-to-netlist) with DFT constraints. Skills Expertise in synthesis and Static Timing Analysis (STA) . Proficiency in writing timing constraints for complex designs. Hands-on experience with post-layout timing closure , including timing ECOs. Expertise in I/O constraint development for various industry-standard protocols. Strong knowledge of EDA tools such as RC, DC, PT, PTSI. Good understanding of VLSI process and device characteristics . Good understanding of deep submicron parasitic effects and crosstalk effects . Qualifications B.Tech. or M.Tech. with relevant experience in Synthesis, STA. Hands-on experience working on technology nodes like 28nm, 20nm, 14nm, 10nm

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and integrating them into full-chip designs. Your expertise in lower technology nodes, physical layout techniques, and verification processes will be crucial for success in this role. You will collaborate with circuit design teams to optimize layout quality and performance, ensuring that layouts meet design matching and parasitic constraints. Working with advanced nodes like 7nm, 16nm, and 28nm, you will play a key role in advancing the company's cutting-edge projects. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ years of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm, 28nm, etc.) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. You will derive circuit block-level specifications from top-level specifications and perform optimized transistor-level design of analog and custom digital blocks. Running SPICE simulations to meet detailed specifications and guiding layout design for best performance, matching, and power delivery will be part of your responsibilities. You will also characterize design performance across PVT + mismatch corners and conduct design reviews at various phases/maturity of the design. Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and possess the required skills, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. This is a full-time, permanent position located in person at Bhubaneswar and Ranchi.,

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ yrs of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm / 28nm ETC) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, where you will be working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Your responsibilities will include deriving circuit block level specifications from top-level specifications, performing optimized transistor-level design of analog and custom digital blocks, running SPICE simulations to meet detailed specifications, and guiding layout design for best performance, matching, and power delivery. Key Responsibilities: - Derive circuit block level specifications from top-level specifications - Perform optimized transistor-level design of analog and custom digital blocks - Run SPICE simulations to meet detailed specifications - Guide layout design for best performance, matching, and power delivery - Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) - Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits - Conduct design reviews at various phases/maturity of the design Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and are interested in these exciting opportunities, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. Join ARF Design for a chance to work on advanced nodes with fast-track interview and onboarding processes.,