Standard Cell Layout Engineer GLOBALFOUNDRIES

10.0 - 15.0 years

3 - 8 Lacs

bengaluru, karnataka, india

On-site

The development of product gradeStandardCellIP covering the following phases: Layout Design ofStandard CellIPs Layout checks likeLVS, DRC,DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side,verificationand validation Layout automation and script support Being a goodteam player,taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support ofsiliconbring up and characterization Required Qualifications: Bachelor s degree with10+years or master s degree with8+years experience in semiconductors / Microelectronics / VLSI engineering. Practical e...

Posted 1 month ago

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Lead Member Technical Staff Siemens EDA (Siemens Digital Industries Software)

3.0 - 7.0 years

0 Lacs

noida, uttar pradesh

On-site

Looking for Siemens EDA ambassadors: Lead Software Engineer for Product Validation and Customer support for PowerPro If you are passionate about innovations that lead to real progress, and if you are curious about technologies that are yet to be developed, then this opportunity might be for you. Utilize your curiosity, passion, and creativity to enhance the lives of millions of people. Join us and share your unique perspective with us! As a valuable member of the Siemens EDA team, your role will involve contributing to the growth of efficiency and customer satisfaction within Siemens EDA's Power platform. This challenging position aims to support the expansion of Siemens's EDA business in In...

Posted 2 months ago

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STA Engineer Finite Hr Consulting

5.0 - 8.0 years

6 - 10 Lacs

Hyderabad, Telangana, India

On-site

This role is for an STA Engineer to be a key contributor in the synthesis and static timing analysis of complex SoCs. The ideal candidate will have extensive experience in timing closure, I/O constraint development for industry-standard protocols, and hands-on experience with advanced technology nodes. Responsibilities Perform synthesis of complex SoCs at both block and top levels. Develop and write timing constraints for intricate designs, including those with multiple clocks and voltage domains. Lead post-layout timing closure for multiple tape-outs, including handling timing ECOs and achieving STA signoff. Develop I/O constraints for industry-standard protocols such as DDR1/2/3, SDR, LPDD...

Posted 2 months ago

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Circuit Design Engineer and Analog Layout Engineer ARF Design Pvt Ltd. - Ranchi

3.0 - 7.0 years

0 Lacs

bhubaneswar

On-site

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and integrating them into full-chip designs. Your expertise in lower technology nodes, physical layout techniques, and verification processes will be crucial for success in this role. You will collaborate with circuit design teams to optimize layout quality and performance, ensuring that layouts meet design matching and parasitic constraints. Working with advanced nodes like 7nm, 16nm, and 28nm, you will play a key role in advancing the company's cutting-edge projects. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Pe...

Posted 3 months ago

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Circuit Design Engineer and Analog Layout Engineer ARF Design Pvt Ltd

3.0 - 7.0 years

0 Lacs

bhubaneswar

On-site

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate ...

Posted 3 months ago

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