636 Silicon Jobs - Page 13

Project description Join our team in developing cutting-edge security firmware for Embedded Systems on Chips (SoCs). You will be working on innovative projects that focus on the security subsystem of silicon, including policy implementation, root of trust, TPM/fTPM, and Widevine. This role demands a high level of expertise in trusted applications and handshakes, contributing to the robustness and security of our products. Responsibilities Develop and maintain security firmware for Embedded SoCs Implement and enhance silicon security subsystems, policies, and root-of-trust mechanisms Work with TPM/fTPM and Widevine to ensure secure communication and data protection Debug and review C code to maintain high-quality firmware standards Collaborate with the team using Git/Gerrit for version control and code review processes Contribute to boot loader and Linux kernel development as needed Skills Must have 3-10 years of experience with MANDATORY Very strong in C language programming and debugging Working knowledge of git/Gerrit Side-band/Out-of-band server management. Experience in OpenBMC based BMC FW development mandatory. Experience on redfish Nice to have Familiarity with boot loader and Linux kernel development Experience with JIRA for project management and issue tracking Other Languages EnglishB2 Upper Intermediate Seniority Regular

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industry s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com Postition Summary: This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities: Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Perform detailed circuit analysis, design, simulation, layout, verification of mixed-mode circuits Interface with foundry partners to understand process details in support of design implementation, manage pixel design and performance, and oversee tapeout and fabrication. Work with test engineers to facilitate development of test hardware, test plans, and oversee chip bring-up and characterization efforts and results. Position Requirements B.S. in Electrical Engineering (M.S./Ph.D. preferred) 6-8 years of experience in practical analog/mixed signal design for image sensors or other relevant areas. Expert at transistor level circuit design, simulation, verification using modern EDA tools from Cadence, Siemens, Synopsys, etc. Knowledgeable in ADC architectures for image sensor readout Relevant experience with bandgaps, bias, op-amps, switched-cap circuits, LDOs, PLL, SERDES, high-speed TX, general feedback, and compensation techniques. Expert in noise analysis, transistor/capacitor matching and sources of errors in analog integrated circuits. Experienced in all stages of mixed-signal chip design (preferably in the context of image sensors) flow including DFT, timing analysis, top chip integration and tapeout, and silicon bring up. Experience leading a design team is highly preferred. Excellent communication skills are required.

THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 18+ years of professional experience in the industry with a proven track record of successfully delivering complex SoCs Sound knowledge of Power delivery and power integrity domains Hands on experience on industry standard tools especially Redhawk based power integrity analysis Should have lead IR/EM convergence on multiple full chip SoCs Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. E view modeling Characterization Verilog behavior modeling, timing lib modeling, Power view modeling, model verification of mixed signal analog IPs like DDR-MSIP, DDRIOs,. SERDES analog, ADC/DAC, PLLs e.t.c. . Functional understanding of mixed signal analog IPs as above for modeling and Characterization verification Proficiency in Verilog modeling and verification. Write behavioral Verilog/Verilog MS/real models of analog blocks. Developing and maintaining the self-checking Test-benches /Test-Plans. SV modeling and testbench development for verification against transistor level netlist Proficiency in Simulators such as VCS e.t.c. 5+ years of experience with characterization tool and simulators like Silicon Smart, Hspice, Finesim, Nanosim and Liberty format description Basic skills on AMS verification and knowledge preferable Self-motivation, teamwork, and strong communication skills. Tcl/Perl/Skill Scripting aware for automation You may e-mail or call Qualcomm's toll-free number found . To all Staffing and Recruiting Agencies :

Role & responsibilities Preferred candidate profile We are seeking a skilled Firmware Engineer to join our team. As a Firmware Engineer, you will be responsible for designing, implementing, and maintaining firmware for embedded systems. The ideal candidate will have strong expertise in embedded controller programming, ESP32 programming, Silicon Labs controller programming, and debugging techniques. You will collaborate closely with hardware engineers and software developers to ensure seamless integration of firmware with hardware components. Responsibilities: 1. Design, develop, and maintain firmware for embedded systems, ensuring reliability, efficiency, and performance. 2. Implement firmware functionalities according to project requirements and specifications. 3. Collaborate with hardware engineers to integrate firmware with hardware components, ensuring compatibility and functionality. 4. Utilize expertise in embedded controller programming, ESP32 programming, and Silicon Labs controller programming to develop efficient and optimized firmware solutions. 5. Conduct thorough testing and debugging of firmware to identify and resolve issues. 6. Optimize firmware performance and memory usage for resource-constrained embedded systems. 7. Stay updated with the latest advancements in firmware development technologies and methodologies. 8. Document firmware design, implementation, and testing procedures for reference and future maintenance. Skills and Qualifications: 1. Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. 2. Proven experience in embedded systems development and firmware programming. 3. Proficiency in embedded controller programming languages such as C/C++. 4. Strong knowledge and experience with ESP32 programming. 5. Familiarity with Silicon Labs controller programming is highly desirable. 6. Solid understanding of debugging techniques and tools for embedded systems. 7. Experience with version control systems (e.g., Git) and collaborative development workflows. 8. Ability to work both independently and collaboratively in a team environment. 9. Excellent problem-solving skills and attention to detail. 10. Strong communication skills, both verbal and written. Preferred Qualifications: 1. Degree in Electronics Engineering, or related field. 2. Experience with real-time operating systems (RTOS) for embedded systems. 3. Familiarity with wireless communication protocols such as Bluetooth, and Wi-Fi. 4. Previous experience in IoT device development projects.

As Product Designer II, you'll design high-impact, intuitive, and scalable experiences for real-world problems in a highly collaborative environment. you'll balance strong systems thinking with executional craft, shaping end-to-end experiences across multiple user journeys, modules, and touchpoints. This role is perfect for a mid-level designer stepping into greater ownership of product and design decisions while influencing product direction through thoughtful, user-centered solutions. Key Responsibilities: Systems Thinking + Strategic Execution: 1. Apply systems thinking to design scalable, modular, and reusable solutions that align with the product architecture. 2. Identify patterns and unify experiences across workflows, reducing redundancy and ensuring platform-wide cohesion. 3. Understand and influence how your work fits into the broader product strategy and business objectives. UX Design Ownership: 1. Own the design process end-to-end: from discovery and research to interaction flows, wireframes, prototypes, and high-fidelity UI. 2. Translate complex workflows and technical constraints into elegant,usable experiences for web and mobile platforms. 3. Balance data-informed decisions with intuition and creative experimentation. Design Systems & Collaboration: 1. Use Tekion s design system thoughtfully and contribute to its evolution by identifying gaps or proposing enhancements. 2. Collaborate closely with engineers, product managers, researchers, and other designers to ensure alignment and delivery quality.Cross-Functional Influence 3. Facilitate collaborative problem-solving using workshops, critiques, and user interviews. 4. Communicate your design decisions effectively to a variety of audiences and adapt your storytelling as needed. 5. Work comfortably in fast-paced environments with shifting priorities.User & Data Focus 6. Advocate for user needs across the product development lifecycle,making tradeoffs based on behavioral analytics, qualitative feedback,and business priorities. 7. Partner with UX research to validate concepts and improve product usability continuously. Skills and Experience 1. 3+ years of experience in end-to-end product design (preferably in B2B or platform-based environments). 2. A portfolio showcasing user-centered, systems-informed design solutions with measurable outcomes. 3. Mastery in Figma and understanding of design system principles, UI patterns, auto-layout, components, and tokens. 4. Experience working across web, iOS, and Android platforms. 5. A clear grasp of product thinking, user psychology, and agile team dynamics. 6. Strong communication and storytelling skills you articulate decisions and rationale confidently across disciplines. 7. Proven ability to navigate ambiguity and proactively clarify problems through a mix of research, collaboration, and iteration. Preferred Skills: 1. Familiarity with the automotive, logistics, or enterprise tech domains. 2. Exposure to data visualization, automation workflows, or messaging platforms. 3. Comfort with cross-touchpoint experiences blending physical and digital interactions. 4. Experience mentoring junior designers or participating in design hiring/interview processes. What We Offer: 1. A world-class team of 75+ designers, working on real industry transformation at scale. 2. A learning-first environment with budgets for conferences, courses, and mentorship. 3. Competitive salary, equity options, and comprehensive medical benefits. 4. Opportunities to grow into Senior Product Designer and beyond through we'll-defined competencies and mentorship. Growth Path: Toward Senior Product Designer: This role sets you up for elevation to Senior Product Designer. you'll be expected to: - Lead with increasing clarity and autonomy. - Solve more complex and strategic problem spaces. - Mentor peers and collaborate across functions at a higher influence level. - Continuously raise the quality bar in craft, process, and systems design. Perks and Benefits: Competitive compensation Generous stock options Medical insurance coverage Work with some of the brightest minds from Silicon Valley s most dominant and successful Companies

Play a critical role in shaping the next generation of AMD products, including CPUs, GPUs, and adaptive compute engines. Interface with large, globally distributed design teams to support complex and collaborative development efforts. Drive automation of Functional ECO methodologies targeting advanced technology nodes. Own the development and support of next-generation synthesis flows, ensuring scalability and efficiency across projects. Collaborate closely with EDA vendors to identify innovative solutions, resolve tool/methodology issues, and enhance flow capabilities. Contribute to the evolution of AMD s design infrastructure by improving automation, performance, and methodology robustness. THE PERSON: You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites and timezones. You have an automation mindset with strong analytical and problem-solving skills, willingness to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsible for developing and automating Functional ECO, Synthesize and PnR flows for various designs at advanced technology nodes. Script out utilities to automate different components of the implementation flow. Support design teams across global sites on various issues related to Front-End Synthesis flow targets. CAD flow and methodology development on advanced process nodes are preferred. PREFERRED EXPERIENCE: Hands on experience in Conformal ECO, Formal Eqv and Front-End Synthesis flows. Hands on experience in industry standard tools such as Conformal, DC, Fusion Compiler, FM,VCLP, ICC2 and Innovus . Hands on experience in any of PnR, STA, Formal Verification or RTL coding domains is a plus. CAD and automation mindset ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering with 3+Yrs of exp

What if companies had truly informed, engaged, and influential employees? This is the challenge that Sociabble decided to take up in 2014, by launching an SAAS platform for Internal Communication , Employee Advocacy , and Employee Engagement . 11 years later, Sociabble is used in more than 180 countries, by companies such as Coca-Cola, Mars, Accor, EDF, Tata, Capgemini, Generali. International since day 1, the company has offices in Paris, Lyon, Boston and Mumbai. Sociabble was founded by two pioneers of the Internet, Jean-Louis B nard and Laurent Gauthier, entrepreneurs and investors for more than 25 years. By building the company, they were inspired by the best of U.S.-based SAAS platforms, without being constrained by the caricatures or culture of Silicon Valley start-ups. They created a boostrapping culture. Sociabble is identified by U.S. analysts as one of the best solutions on the market today. Simplicity, kindness, respect, exemplarity, fairness, and trust are the values around which the company has developed. The teams consist of a mix of experienced and junior professionals, to facilitate day-to-day learning through mentoring. The mission You ll join the Customer Success Management (CSM) team , within the Customer Success Technical Architect (CSTA) unit , which currently includes two members based in France. As the first CSTA in India, you ll integrate our SaaS solution into client environments while collaborating closely with your colleagues in France. This position focuses on: Developing a deep understanding of the platform and its features Ensuring the successful launch of new client projects by managing all technical aspects of the product s integration into client information systems Assisting Sales/Presales teams on technical topics (APIs, SSO, security, GDPR), including RFPs Establishing yourself as a technical expert and primary contact for client IT departments Providing ongoing technical support to CSMs and external stakeholders throughout the project Collaborating with the Support and Product teams, acting as a bridge between client needs and internal solutions Centralizing and documenting integration and deployment specificities across client projects This role calls for technical proficiency, independence, and a strong client-oriented mindset , fostering collaboration across CSM, Product, Legal, and Sales teams! The ideal candidate You specialize in IT Project Management with a solid technical development background You have 3 to 10 years of experience managing technical, client-facing projects, including regular calls with Enterprise clients You re comfortable working with Enterprise IT teams , understanding their technical constraints and challenges You can navigate complex, interconnected products You know one or more web languages ( HTML, CSS, JavaScript, PHP ) and are familiar with integration concepts ( SSO, APIs ) You re confident using automation tools (e.g., Power Automate) and reading technical documentation Your organizational skills and attention to detail help you manage multiple projects simultaneously You adapt your communication style to suit both technical teams and C-level audiences , thanks to strong teaching abilities You thrive on problem-solving and enjoy tailoring solutions to meet client needs You are fluent in English ; knowledge of the SaaS environment is a plus You re used to working in a multicultural environment The perfect match? You will thrive at Sociabble if You have a strong taste for new technologies, the world of SaaS and digital transformation, and wish to practice in a constantly evolving environment. You are looking for a job with strong responsibility coupled with freedom of initiative, and would like to get involved in an ambitious project. You wish to participate in an adventure and grow with an ambitious and benevolent team with globally recognized companies to ensure their satisfaction with their projects. You like international, transparent environments where everyone can learn and be heard. Our perks Join an international SaaS scale-up certified as a Great Place to Work and recognized among the Best Workplaces in 2023. Enjoy benefits designed for your well-being at work: healthcare support, paid leaves , sick days, and paid leaves for family reasons . Find your perfect balance with hybrid and flexible work (#LI-Hybrid), all while reuniting with your team in our beautiful office in Bombay each Thursday. Connect with your colleagues through numerous events : afterworks, team buildings, town halls. Choose a committed company : partnership with Tree Nation, where each Sociabble employee plants trees to offset their CO2 emissions. Embody our values : kindness, ambition, humility. At Sociabble, we are Bootstrappers . Recruitment Process HR Interview (45 min - video call) with Camille 1.5-hour written assessment (to complete on your own) Manager interview (1 hour - video call) with Benjamin Head of Asia interview (30 min video call) with Krusha Reference check Explore your new role with personalized and comprehensive onboarding, followed by workshops, Friday trainings, and year-round training sessions! Important information before applying Permanent Position Based in Mumbai or Bangalore All your information will be kept confidential according to EEO guidelines.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Are you ready to combine the fast-paced energy of an innovative startup with the resources and stability of a global tech leaderThis opportunity blends both worlds into one. Edge Impulse has joined forces with the Industrial Embedded IoT division of Qualcomm, and we are growing our team because Edge AI is an important part of Qualcomm’s diversification roadmap. Edge Impulse streamlines the creation of AI and machine learning models for edge hardware, allowing devices to make decisions and offer insight where data is gathered. Powerful automations make it easier to build valuable datasets and develop advanced AI for edge devices from MCUs to CPUs to GPUs. The ease of use and versatility that Edge Impulse provides supports customers launching AI-empowered devices globally to solve the planet's biggest problems with novel high-tech solutions. Used by health and wearable organizations, industrial organizations, as well as top silicon vendors, Edge Impulse has become the trusted ML platform for enterprises and developers alike. As a Developer Relations Engineer at Edge Impulse, you will play a pivotal role in engaging, educating, and supporting the developer community. The primary focus is to drive awareness and adoption of Edge Impulse’s edge AI technology through a combination of technical content, community engagement, and hands-on development. This role bridges the engineering team and the broader developer community. Empower developers to build, optimize, and deploy edge AI models effectively with our platform. This role offers immense potential for growth, learning, and impact within a collaborative and inclusive team. Primary Responsibilities Responsibilities span multiple domains – from Community Engagement to Content Creation and Developer Advocacy – it takes creativity, resilience, and willingness to learn Grow and nurture the Edge Impulse developer user base through the creation and maintenance of external technical documentation content of the Edge Impulse platform and features Create and present workshops, videos, webinars, demos for engineering conferences and developer events to represent Edge Impulse to the wider developer community and grow user engagement. Preferred Skills and Experience A minimum of 5 years in Developer Relations, Developer Advocacy, or a similar role, with a focus on AI and IoT solutions A minimum of 5 years of relevant experience in technical writing Proven professional experience in public speaking to technical audiences Excellent communication and presentation skills to explain complex technical concepts to diverse audiences Clear track record with community engagement such as managing user forums, handling technical questions from other developers, and running developer-focused workshops Proficiency in languages commonly used in ML and edge AI (e.g., Python, C++) and familiarity with ML workflows and deployment. Experience with LLMs and VLMs is a plus Experience creating technical content, including blog posts, tutorials, videos, and documentation Demonstrated ability to build and nurture developer communities, both online and offline Some experience with video production and exposure to social media best practices, usage of various social channels, and presence on key channels Fluency in a second or third language is highly valued Academic Credentials Master’s degree in engineering, computer science, or other relevant field preferred Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world’s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (16+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Excellent Design verification domain expertise. Develop test strategy, TB architecture and test plan for new IP’s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Grow with us We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What We Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced design technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. What you will do Key Responsibilities: Develop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology. Take full ownership of a design, whether at the block or subsystem level. Generate comprehensive documentation throughout the design lifecycle. Perform digital design and conduct all RTL sign-off checks. Continuously enhance and optimize design methodologies and processes. Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. Work closely with verification engineers to review and refine verification plans. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor s degree in electrical or computer engineering. 5+ years industry experience in ASIC design. Additional experience will allow placement at higher job levels. Strong Experience in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions. The skills you bring Additional Requirements: Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Expertise in low-power design, including specifying power intent using UPF or similar standards. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768630

SE NIOR SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, implement, and execute the Physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and Implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. PREFERRED EXPERIENCE: 5+ Years of experience in relevant domain. Experienced with Blocklevel and Toplevel Physical implementation. Good understanding and hands-on experience in Lower node technologies. (7nm/5nm or below) Preferably working on Lowpower or processor designs. Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.., Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

About Us: Neuron7.ai is a rapidly growing AI-first SaaS company focused on building a category-defining service intelligence product. Backed by leading venture capitalists in Silicon Valley and a distinguished group of angel advisors/investors, we are recognized as a startup to watch. Our platform empowers enterprises to make accurate service decisions at scale by delivering service predictions in seconds through the analysis of structured and unstructured data. Learn more at Neuron7.ai . Why Join Us: At Neuron7.ai , you ll be part of a dynamic and innovative team that is redefining service intelligence. We value creativity, collaboration, and a commitment to pushing boundaries. About the Team: The product team at Neuron7 is new and growing! You ll join a design + product team working to launch Neuron7 s next wave of innovation and to establish a design and research practice at Neuron7. As an early member of the team, you ll have the opportunity to have significant impact on both product direction and on the team s design culture. Most of Neuron7 is based in either the Bay Area andBangalore. What you ll do: Neuron7 is building the next generation of AI-powered service intelligence, enabling enterprises to improve service efficiency and predict future issues before they occur. As the Product Designer for Search, you will craft the user journey around our Search product and corresponding analytics and insights and elevate the design quality across our products. You ll collaborate with Product, Data Science, Engineering, and Customer Success teams to improve both knowledge and diagnostics search as well as provide insights on search KPIs to our customers. Your work will empower organizations to accelerate troubleshooting, answer any questions, and optimize service workflows. Own the end-to-end design process for Next Gen Search product, including discovery, ideation, prototyping, high-fidelity UI, and implementation support Partner with Product and Engineering to define and execute the product strategy and roadmap to ensure intuitive and scalable user experience Work closely with the Head of Design to establish design vision and principles for the Neuron7 platform Conduct or support user research and usability testing to understand user needs, validate ideas, and iterate quickly Contribute to the creation of a design system that supports efficiency, consistency and high-quality design across the platform Work autonomously while collaborating in person with cross-functional peers in Bangalore and asynchronously with global stakeholders What We re Looking For 8+ years of product design experience, with a strong portfolio of delivering consumer-level experience in complex B2B or enterprise products High agency. Proven ability to own and drive the end-to-end design process Strong design craft with attention to detail in interaction, usability, and visual design Expertise in Figma and passionate about learning the latest design and AI tools to continue evolving the design practice Excellent collaboration and communication skills, bringing people along through storytelling, prototypes, and clear rationale Self-starter who thrives in fast-paced, high-growth environments Experience working with cross-functional partners to ship high-quality product experiences Familiarity with user research and a deep passion for deeply understanding customer pain points Excited to work on cutting-edge AI technology and help define a category: Service Resolution Intelligence Passion for solving real-world problems with innovative, AI-powered solutions If this sounds like you, we want to hear from you! Come join a high-impact team where your voice and ideas will shape what we build and how we build them!

Confiz is hiring: Senior Software Engineer- React JS & Angular Senior Software Engineer- React JS & Angular We are seeking a skilled Senior Software Engineer- React JS & Angular to join our dynamic team Confiz is looking for candidates with 3+ years of experience: Responsibilities: Responsible for the development, deployment, and maintenance of React JS & Angular web applications Primary focus will be development of web applications and their integration with back-end services Will be working alongside other engineers and developers working on different layers of the infrastructure. Commitment to collaborative problem-solving, sophisticated design, and the creation of quality products is essential. Translate designs, wireframes, and mockups into highly composable code Ensure the performance, quality, and responsiveness of applications Collaborate with a team to define, design, and ship new features Identify and correct bottlenecks and fix bugs Help maintain code quality, organization, and automation Deployments using docker containers Requirements: Must-have: 3+ years of hands-on experience in React JS and related ecosystems (Web pack, Redux, ES6, Flow, Jest) Working experience with Angular 9+ Strong JavaScript concepts and design patterns. Experience with docker and containers Experience working with Rest APIs Experience with performance and memory tuning with tools Experience with NPM/Yarn Experience with a project tracking tool like JIRA Familiarity with UX concepts (Responsive, Mobile first) Proficient understanding of code versioning tools (GIT will be preferred) Familiarity with continuous integration and GitHub pipelines We have an amazing team of 700+ individuals working on highly innovative enterprise projects & products. Our customer base includes Fortune 100 retail and CPG companies, leading store chains, fast-growth fintech, and multiple Silicon Valley startups.

About Marvell . Your Team, Your Impact Marvell innovates in Ethernet switching technology across a broad portfolio of segment-focused product families. Marvell switches power next-generation campus, industrial, 5G, cloud and AI networks. What You Can Expect Develop and document SW features for a software development kit. Deliver SW releases, sample codes, and patches to customers and involved in the SW integration into their platform. Troubleshoot complex software problems (SW API, GUI, SW Tools/Drivers) and recommend corrective action. Closely follow and check customer technical issues, provide remote or on-site troubleshooting. Support customer lab/field trial, able to understand customer application environment and provide insightful advice on customer products. Help/train customer to understand Marvell product architecture and features, promote and demo Marvell products functionalities with Sales and Marketing. Work cross functionality with silicon development, system validation, and marketing team to deliver SW solution. Develop technical collateral material including application notes, user guide/manual, release notes, white papers and other technical documents. Articulate technology and product positioning to both business and technical users. Assist sales team through preparation and delivery of technical presentations and statements of work by matching specific client business requirements with effective technical solutions. Create relationships with key decision makers and serve as external technical spokesperson. Provide customer feedback to executive and development teams to participate in functionality roadmap planning. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience. Must possess excellent written and verbal communication skills. Be able to present and clearly articulate solutions to customers. Previous experience of working as an Application Engineer or any equivalent Customer interacting role (i. e. ability to handle customers) is a must. 5-10 years of experience in networking, with a focus on AI infrastructure. 5 - 10 years of experience in customer-facing roles, providing technical support and solutions. Preferred Qualifications: Experience with switch driver development and community software such as SAI/Sonic. Proficiency in developing and debugging device drivers and silicon. Understanding of system-level switch and hardware requirements. Familiarity with networking protocols and VLSI design. Strong leadership and communication skills, with the ability to inspire and guide teams. Working with internal and external customer teams. Wide knowledge in code review, debug, and preparing patches. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1

Performance Benchmarking Lead Job Description We are seeking an experienced engineer to lead Performance Benchmarking of RISC-V CPUs. This position requires a candidate with knowledge and interest in performance benchmarking, computer architecture, and experience working on pre- and post-silicon platforms. The candidate will contribute to the advancement of MIPS high-performance designs through their benchmarking and analysis work, as part of the MIPS Performance and Architecture team. Responsibilities Provide Technical Leadership to a team of Performance Benchmarking engineers. Create and maintain the infrastructure to carry out benchmarking on RTL Simulation, FPGA and Silicon. Carry out Competitive Analysis and Research industry trends. Analyze and debug performance issues. Work closely with Product and Design teams to help improve performance of MIPS products. Ideal Candidate Profile Strong Background in Performance Benchmarking and CPU Microarchitecture. Familiarity with industry standard benchmarks including SPEC, Lat-mem, Stream. Background in programming - C, Python. Hands-on experience working with FPGAs, Boards, Linux. Hands-on experience setting up and improving automation frameworks. Prior experience in leading teams. Plus Familiarity with microarchitecture constructs - for e.g. TLBs and caches. Experience with RISC-V and,or MIPS CPU architecture. Linux Kernel experience. Compiler toolchain experience.

Grow with us We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What We Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced design technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. What you will do Key Responsibilities: Develop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology. Take full ownership of a design, whether at the block or subsystem level. Generate comprehensive documentation throughout the design lifecycle. Perform digital design and conduct all RTL sign-off checks. Continuously enhance and optimize design methodologies and processes. Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. Work closely with verification engineers to review and refine verification plans. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor s degree in electrical or computer engineering. 5+ years industry experience in ASIC design. Additional experience will allow placement at higher job levels. Strong Experience in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions. The skills you bring Additional Requirements: Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Expertise in low-power design, including specifying power intent using UPF or similar standards. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Primary country and city: India (IN) || Bangalore Req ID: 768630

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 3 years of experience with functional tests for silicon validation (e.g., C, C++ or Python) or developing embedded software.. Experience in silicon bring up, functional validation, characterizing, and qualifying silicon.. Experience with board schematics, layout, and debug methodologies using lab equipment.. Preferred qualifications:. Experience in hardware/software integration (i.e. pre-silicon use of emulation and software-based test and diagnostics development).. Experience in scripting languages, such as Python for Automation development.. Experience with Power Characterization, PCIe, DDR.. Experience in RTL design, verification or emulation.. Knowledge of SoC architecture, including boot flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will be responsible for post-silicon validation of the Cloud TPU projects. You will create test plans and test content for exercising the various subsystems in the AI/ML SoC, verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work closely with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver quality designs for next generation data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.. Responsibilities. Develop and execute tests in post-silicon validation and on HW emulators and assist in bring-up processes from prototyping through post-silicon validation.. Drive debugging and investigation efforts to root-cause cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bring up and production.. Ensure validation provides necessary functional coverage for confident design.. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 5 years of experience in architecture, hardware, digital design, and software co-design. 3 years of experience in Verilog/SystemVerilog.. Experience in computer architecture and digital design or Internet Protocol (IP) integration (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory).. Preferred qualifications:. Master's degree in Electrical Engineering, Computer Science, or a related field.. 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory, Gigabit Ethernet, Flash).. Experience in developing architectures for Machine Learning Accelerators.. Experience in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, waveform debug skills with knowledge of chip design flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will integrate hardware and software stacks and operate them on emulation platforms for pre-silicon validation of our Google Cloud Tensor Processing Unit (TPU) projects. You will create software-based custom test cases, workloads, test generators, infrastructure, analysis tools, and debugging tools. You will be responsible for silicon bring-up, validation, characterization and qualification, and sustaining programs and their quality. You will help ensure our fleet runs at maximum efficiency, and help debug and root when causing issues. You will collaborate with Product Firmware, System Software and Application-Specific Integrated Circuit (ASIC) Design in the development of tools, validation firmware, functional and performance tests, and testing infrastructure for our platforms and Google Cloud data center systems.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.. We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.. Responsibilities. Enable bring-up of chip features through firmware and driver stack. Integrate and validate hardware and software designs in pre-silicon.. Architect and design Application-Specific Integrated Circuit (ASIC) models for Emulation/Field Programmable Gate Array (FPGA) Prototypes. Design Register-Transfer Level (RTL) transformations to optimize mapping to Emulation/FPGA platforms and design solutions to improve Internet Protocol (IP) modeling.. Design solutions to improve hardware modeling accuracy and scale to various system configurations and enable serving of ASIC models for software and validation teams.. Bringup chip features on software reference models and hardware prototypes (e.g., Emulation/FPGA) and drive debug discussions with design/design validation/physical design/software/architecture teams and help root-cause failures.. Develop the integration plan with software and system partners, coordinate hardware and software delivery and benchmark performance.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR).. Experience in silicon bringup, functional validation, characterizing, and qualification.. Experience with board schematics, layout, and debug methodologies with using lab equipment.. Preferred qualifications:. Experience in hardware emulation with hardware/software integration.. Experience in coding (e.g., Python) for automation development.. Experience in Register-Transfer Level (RTL) design, verification or emulation.. Knowledge of SoC architecture including boot flows.. Knowledge of HBM/DDR standards.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will be responsible for post-silicon validation of the Cloud Tensor Processing Unit (TPU) projects. You will create test plans and test content for exercising the various subsystems in the Artificial Intelligence/Machine Learning (AI/ML) System on a Chip (SoC), verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver high-quality designs for next generation data center accelerators.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.. We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.. Responsibilities. Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation.. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production.. Ensure validation provides necessary functional coverage for skilled design.. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring block/SS level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 3+ years of experience for timing closure of block/SS Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. Good understanding of SDC construct ( clock generation , false path , multi cycle paths..) ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering