636 Silicon Jobs - Page 15

Opportunity for a talented individual for their memory interface products. We are looking for a candidate with a strong background in verifying complex integrated circuits. The candidate needs to have skills that are up to date with the latest IC verification tools and flow. The candidate will work closely with design, and verification engineering. In addition, strong collaboration and communication skills are a must. Duties/Responsibilities: Develop verification testbench components for chip/module level using SystemVerilog. Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment. Define and execute detailed verification plan from spec working with architects and designer engineers Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out. Debug tests, and regression failures. Participate in silicon debugging and analysis. Qualifications MS in Computer or Electrical Engineering with a minimum of 5+ years of experience in design/verification management of highly complex projects. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM). Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is preferred. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Design and implementation of Interconnect for next gen SoC design. Work with System architects and IP design owners to understand requirements for optimal implementation of interconnect. Prior experience with Arteris Flexnoc/NIC/NoC will be an added advantage. RTL development including tool flows like lint, CDC and synthesis. Knowledge of standard bus protocols mandatory for efficient interconnect design. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. Provide support to SoC integration and chip level pre/post-silicon debug. Work closely with Functional verification, performance verification and emulation teams to ensure all requirements are verified in pre Silicon environments. Provide post Silicon support related to device performance to validation and SW teams. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 12+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc. ), synthesis/DFT/FV/STA. Ability to understand IP needs and translate to optimal Interconnect design needs. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role and Responsibility: The Functional Safety Engineer will be responsible for the ISO 26262 safety plan implementation for the Silicon Solutions Group (SSG) IPs (including but not limited to processors, hardware accelerators and controllers) targeted for automotive products, and development of ISO 26262 compliant processes, infrastructure and work products. He/she will work with the safety organizations of our customers, vendors, external safety expert consultants and internal product development teams to ensure that the functional safety process is well understood, executed and documented. This role will be an integral part of an agile engineering team that focuses on bringing safety and cybersecurity solutions per the ISO 26262 and ISO 21434 standards to Cadence customers in the fast growing Automotive/ADAS markets. This individual will support the organizations mission, vision, and values by exhibiting the following behaviors: excellence and competence, collaboration, flexibility, innovation, respect, accountability, ownership, and a sense of humor. Specific Duties and Responsibilities: Act as Functional Safety Engineer for Cadence/SSG Safety related HW SW products Create and/or support functional safety work products according to ISO 26262 which include the Safety Plan, Safety Manual, Safety Requirements, and Safety Analysis including qualitative and quantitative FMEDA, and Safety Verification and Validation activities on SSG IPs as a SEooC (Safety Element out of Context). Collaborate with project engineers, marketing development team, safety consultants, vendors and customers on Functional Safety activities Work with architecture team on Functional Safety products to propose safety features and define the safety architecture Create/review functional safety documentation according to ISO 26262 Conduct reviews with product teams to ensure functional safety standards are being met throughout product development cycles Requirements: BSEE/BS Computer Science, Computer Engineering, Electrical Engineering (or equivalent). MS preferred. 5 or more years of total relevant work experience. Experience or familiarity with Microprocessor, DSP, hardware accelerator and hardware accelerator architecture/design and verification processes, SoC/ASIC design methodologies (RTL and Synthesis). Willingness and motivation to learn and apply standard compliance requirements of emerging markets Strong analytical and problem-solving skills and clear, concise documentation writing skills Excellent verbal and written communications skills and the ability to communicate complex ideas succinctly and persuasively to peers, management, customers and partners. Good To Have: Experience in ISO 26262, safety certification strongly preferred. Experience in FMEDA, DFA, FMEA, FTA Proven record of taking customer safety requirements from concept to final product Scripting, programming and process automation skill Experience in fault injection techniques Familiarity with Configuration, Requirements, and Documentation Management tools (e. g. Perforce, Jama, JIRA, etc) Knowledge of ISO 21434 Knowledge of ISO 9001 Quality Management standard Experience with embedded HW/SW systems Product Development Life Cycle (Processors, Software) Travel : Occasional travel, including international travel, may be required. Work Environment: Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. The annual salary range for California is $136, 500 to $253, 500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We re doing work that matters. Help us solve what others can t.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industrys most complex semiconductor chips. What youll be doing: As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression. Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features. In addition, you will help develop and deploy DFT methodologies for our next generation products. Be apart of innovation to strive improve the quality of DFT methods. You will also need to work with multi-functional teams to incorporate DFT features into the chip. Occasional travel and also some late hours online meetings involved during critical milestones. What we need to see: BSEE or MSEE from reputed institutions or equivalent experience. 2+ Years of experience preferably in Design for testability (DFT) You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design. Experience in RTL and Gates verification and simulation. You need to be familiar with BIST architecture and JTAG/IEEE1149. 1/IEEE1500. Strong DFT knowledge in Scan ATPG, compression techniques and memory test. Strong analytical and problem solving skills. Expert coding skills in industry standard scripting languages. Extraordinary written and oral communication skills with the curiosity to work on rare challenges. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If youre creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you ll be doing: Work on structural and functional verification of low power aspects of NVIDIA s family of chips. Come up with test plans and coverage plans of these features. Write test cases, test bench components like assertions and coverage points, and own verification convergence. Collaborate with system level and unit level teams to cover the features well from functional, electrical, performance, and noise aspects. Work with architects, designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Validate the effectiveness of the low power features on silicon. What we need to see: BS/MS or equivalent experience with specialization related to Low Power techniques and Verification. 2+ years of experience. Fundamental understanding of power basics including transistor-level leakage/dynamic characteristics of VLSI circuits. Knowledge of power intent formats - UPF/CPF. Experience in Static Power check - tools like VCLP/MVRC or similar. Hands-on knowledge in Power aware dynamic verification - NLP/MVSIM or similar tools. Experience in design and verification tools (VCS or equivalent simulation tools, Verdi or other debug tools). Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS). Ways to stand out from the crowd: Good software programming skills. Python/Perl/C++ preferred. Confident debugging and problem-solving skills. Good communication skills and ability desire to work as a great teammate. With competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. #LI-Hybrid

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Why join Ericsson What happens once you apply Primary country and city: India (IN) || Bangalore Req ID: 768586

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Why join Ericsson What happens once you apply Primary country and city: India (IN) || Bangalore Req ID: 768584

Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high performance memory interface in the world. As a memory subsystem design verification engineer, youll be responsible for all aspects of digital verification such as functional, performance, DFD and DFT features around DDR and HBM memory subsystem designs. Responsibilities Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design Work closely with 3rd party IP vendors to validate the correctness of integration and custom features. Develop testplan and testbench Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of testbench Develop test stimulus, checkers and scoreboard in SystemVerilog/UVM Debug, regression and coverage closure Provide debug support to emulation and silicon-bring up teams. Able to work with teams across the continents Key Qualifications Hands-on experience of verifying digital logic portion of DDR/HBM memory subsystem design Knowledge in JEDEC specification of LPDDRx/DDRx/HBMx Knowledge in the DDR DFI specification and protocol Knowledge in Reliability, availability and serviceability (RAS) features in the context of memory subsystem such as Error detection/correction and Encryption Education and Experience Master s Degree or Bachelor s Degree with 3-5 years of experience

Role: CAD Engineer (Frontend and Backend) Experience: 10+years Location: Bangalore Notice Period: Max 15days preferred Role Overview We are looking for a CAD Engineer (Frontend and Backend)to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What youll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure. Key Responsibilities: Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets. Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime. Analyze and resolve timing violations, with a focus on test modes and scan paths. Integrate and validate timing constraints from third-party IPs and external vendors. Generate detailed timing reports, highlighting violations and providing optimization recommendations. Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues. Contribute to the development and enhancement of STA methodologies, flows, and automation. Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision. Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind. Collaborate effectively with cross-functional and globally distributed teams. Basic Qualifications: Bachelor s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master s degree with 6+ years. Proven experience with block- and full-chip timing constraints, including test modes. Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT. Experience integrating third-party IPs and managing associated timing constraints. Proficiency in STA tools such as PrimeTime and scripting for automation. Preferred Qualifications: Experience with automated constraint generation and validation tools. Familiarity with high-speed interfaces such as PCIe, CXL, and DDR. Strong communication and collaboration skills in cross-functional, globally distributed teams. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Who We Are Simpplr is the AI-powered platform that unifies the digital workplace - bringing together engagement, enablement, and services to transform the employee experience. It streamlines communication, simplifies interactions, automates workflows, and elevates the everyday experience of work. The platform is intuitive, highly extensible, and built to integrate seamlessly with your existing technology. More than 1,000 leading organizations - including AAA, the NHS, Penske, and Moderna - trust Simpplr to foster a more aligned and productive workforce. Headquartered in Silicon Valley with global offices, Simpplr is backed by Norwest Ventures, Sapphire Ventures, Salesforce Ventures, and Tola Capital. Learn more at simpplr.com . About the Role Join our forward-thinking team as a Data Scientist, where you will address real-world challenges through the lens of AI innovation, specifically focusing on Enterprise Search, Personalization, Content Recommendation, and pioneering work with custom LLM fine-tuning. Work in an environment that fosters collaboration among highly skilled professionals to build next-generation products that significantly impact our clients operational effectiveness. Key Responsibilities Innovate and develop scalable solutions leveraging AI technologies to process and analyze vast amounts of data efficiently. Quickly prototype, test, and deploy effective AI solutions, managing project timelines and deliverables while incorporating the latest advancements in AI research. Engage with cross-disciplinary teams to identify and implement AI-driven enhancements for user experiences, leading the charge from ideation to deployment. What We re Looking For 1-3 years of experience in crafting and implementing AI models, with a particular interest in applications within Enterprise Search and Content Personalization. Solid grounding in AI technologies, with proficiency in Python and familiarity with AI development frameworks. Interest or experience in ML-Ops, emphasizing the journey from concept to production scalability of ML models. Openness to candidates with a robust background in backend development who have delved into AI, especially those who have engaged in Enterprise Search, Developing learning to rank models, Agentic Workflows and LLM fine-tuning. Knowledge in developing analytical applications and working with cloud platforms, capable of managing large data sets and complex AI models. Technical skill sets Strong coding skills Understanding basics of Machine Learning, Deep Learning, and Natural Language Processing algorithms Experience in working with data annotation tools and building ML evaluation pipelines Comfort with working in multiple tech stacks Experience in API Development, Docker and AWS Services Education - Bachelors degree from a Tier-1 college (IITs, NITs, BITS, or equivalent preferred). Nice to have: Experience in ML research, focusing on LLMs, Information Retrieval Systems, Reinforcement Learning, Knowledge Graphs, Agentic Workflows, Retrieval-Augmented Generation (RAG), Recommender Systems, Scaling, Monitoring, and Deploying LLMs Our Ideal Candidate We are in search of individuals who are not merely experienced but deeply passionate about unearthing new challenges and inquiries in the realm of AI. We value creativity, positivity, work ethic and the pursuit of answering intricate questions with methodical accuracy. Multiple positions at different seniority levels are available. Simpplr s Hub-Hybrid-Remote Model: At Simpplr we believe that when work is good, life is better and that belief guides all we do. Including how we approach our flexible work model. Simpplr operates with a Hub-Hybrid-Remote model. This model is role-based with exceptions and provides employees with the flexibility that many have told us they want. Hub - 100% work from Simpplr office. Role requires Simpplifier to be in the office full-time. Hybrid - Hybrid work from home and office. Role dictates the ability to work from home, plus benefit from in-person collaboration on a regular basis. Remote - 100% remote. Role can be done anywhere within your country of hire, as long as the requirements of the role are met.

Company Description : Nexthop AI is a team of industry-leading professionals with deep hardware and software expertise spanning silicon, systems, network operations and cloud development, dedicated to building innovative, bleeding-edge solutions for large-scale AI deployments. The team culture thrives on collaboration, creativity and fun while delivering foundational technologies for next-generation AI infrastructure. About the Role: We are seeking an experienced Technical Content Strategist/Developer to be an integral part of our team. Job Responsibilities: Collaborate with cross-functional teams hardware and software engineers, product managers, technical support engineers, customer engineers to gather technical information, verify content accuracy, and convert it into different forms of technical content. Develop and maintain customer-facing technical product documentation, including configuration guides, product manuals, CLI guides, release notes, and training material. Ensure that our technical content is clear, concise, and actionable, and tailored for our target audiences network architects, operators, and data center engineers. Practice and implement documentation standards, best practices, templates, versioning and style guides. Create and / or polish content for our corporate website, blog, and customer portal. Leverage AI tools and automation workflows to make content development and editing more effective and efficient and content easily queryable by users. Qualifications : Were seeking individuals who thrive in a fast-paced, collaborative startup and have a strong aptitude for taking initiative and learning. Additionally, we value individuals who practice and instill customer empathy. 8+ years of experience as a technical writer, content developer, or similar role. Strong background in networking and familiarity with data center technologies. Exceptional writing, editing, and proofreading skills. Excellent collaboration skills and experience of working with crossfunctional teams both local and remote. Ability to translate complex technical concepts into clear, concise, and customer-friendly content. Working knowledge of modern enterprise documentation platforms such as Docusaurus, Document360, or Gitbook, and structured authoring tools such as DITA, Markdown, or Oxygen. Demonstrated experience of using AI tools to assist with information retrieval, research, content creation, and process automation. Experience of creating technical documentation for networking products both hardware and software. Familiarity with modern headless CMS solutions such as Contentful, Sanity, and Strapi, and web technologies such as Wordpress, HTML/CSS, and Javascript/React would be a big plus.

Title: Memory IP Design Engineer- (eFuse) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 4-20 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . Required Skills: Strong software development and architecture skills (Python, C# or similar) Hands-on experience with test and measurement equipment, measurement techniques and test automation Firmware development skills (C and/or assembly language) Strong analog and digital circuit analysis skills Excellent troubleshooting and debug skills Self-driven with a strong work ethic and sense of accountability Experience Level: 4- 6 Years i n Industry Preferred Skills: Knowledge of ARM/8051 architectures and typical MCU peripherals Experience with schematics capture and layout tools (Allegro/Altium/PADS) Post-silicon validation experience Exposure to security standards and security testing Personal profile : Enthusiastic and curious, likes to figure out how things work and prove it Methodical, thorough and dedicated to quality Good verbal and written communication skills Comfortable with cooperating across functional groups Entrepreneurial and problem solver Team player Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

MTS SOFTWARE SYSTEM DESIGN ENGINEER THE ROLE: The right engineer will drive the success of power IP (Intellectual Property) and features in AMD (Advanced Micro Devices) products through leadership & coordination, resolution of technical dependencies, and achievement of schedule commits. This is a high-visibility and widely multi-functional role, spanning pre-silicon architecture to post-silicon implementation & product delivery. THE PERSON: Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers. KEY RESPONSIBILITIES: Own the multi-functional Power Feature Enablement team for new AMD APU (Accelerated Processing Unit) products Work across engineering teams and subject areas spanning silicon, firmware, hardware, and software Coordinate debug of issues and drive them to closure Pull together meetings, set up clear agendas and follow up on action items Deliver regular progress updates toward program goals Make tough decisions such as priority calls based on partial or incomplete data Proactively drive continuous improvement for post-silicon power and performance activities Must be a self-starter, and able to independently drive tasks to completion PREFERRED EXPERIENCE: Product development or systems engineering background with hardware platforms and their software & firmware ecosystems Excellent verbal communication and written, presentation skills Excellent interpersonal, organizational, analytical, planning, and technical leadership skills Proven record of accomplishment in delivering large multi-functional product solutions Experience working in a fast-paced matrixed technical organization and multi-site environment Product or program management ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer or Electrical Engineering or equivalent Benefits offered are described: AMD benefits at a glance .

Post Silicon & System Validation Engineer The Battery Management System team within the automotive BU is looking for a highly skilled Silicon and System Validation Engineers based in Bengaluru, India who will be responsible for executing the silicon and system validation activities for our next generation of high-performance product portfolio. Context on the role: As a Silicon Validation Engineer, you will perform a full range of product development activities including, but not limited to: Job Duties: Understand the product requirements, develop and execute the BMS IC validation plan Apply the domain knowledge of BMS systems and customer insights into product validation plan development and execution. Design and build custom test hardware to evaluate the battery management silicon and system products. Debug and resolve system issues with cross functional team from design, test, and applications. Collaborate in a dynamic team environment to learn and deploy best practices in application development Requirements*: BS/BEE or MTech in Electrical Engineering, Electronics Engineering with 5 to 8 years of Industrial work Experience in the post silicon validation. Experience developing test plan, test cases, building test environment and executing test plans against silicon and system level specifications.

Participate in the development and testing of Field-Programmable Gate Arrays (FPGAs) for various projects. In your new role you will: Experience with FPGA design and development Proficiency in Vivado and other design software Providing Simulation of digital designs and design FPGA board Design emulation circuits for analog parts with discrete device Experience with lab equipment and testing procedures Validating on lab testing of FPGA Strong understanding of digital and analog circuit design Strong analytical and problem-solving skills You are best equipped for this task if you have: Master s or Bachelor s Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in FPGA design, preferred with Xilinx/Vivado. Experience in digital and mixed-signal design, particularly with System Verilog. Good Analytical skills and good understanding of digital and mixed signal designs. Familiarity with power conversion topologies, such as DC/DC and AC/DC converters, is highly desirable. Experience in pre-silicon verification would be a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Contact: Garima Chauhan - garima,chauhan@infineon.com We are on a journey to create the best Infineon for everyone.

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Primary country and city: India (IN) || Bangalore Req ID: 768584

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive Full chip physical integration and verification (DRC/LVS, ERC, DFM checks) Work with fab and fab contacts for all the tapeout activities leading to final tapeout. Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: Experience : More that 12 years of relevant experience. Driven multiple tapeouts across different technology nodes Sound knowledge of full chip physical integration and verification flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Title: Memory IP Design Engineer- (eFuse) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 4-20 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills.

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In this position, the individual will be responsible for full ownership of supply planning and customer order fulfillment for a particular product line. The role would involve working with product management, engineering, procurement, silicon planning, demand planning, capacity planning, sales operations, business teams, supply chain process teams, and IT to ensure closure of the supply plan to meet demand within the planning horizon. Responsibilities include analyzing and resolving the daily plan output for supply to demand mismatches, producing weekly material and capacity plans to the factories, weekly closure of excess and obsolete inventory, and daily closure of inquiries from internal customers. Additionally, the individual should possess strong analytical skills to enhance and automate existing processes and contribute towards digital transformation the supply chain planning. The individual must be technically strong while handling planning or production activities and should be comfortable while conferring with management personnel regarding supply availability, purchases, product specifications, manufacturing capabilities, and project status updates. The individual must possess exceptional interpersonal and team building skills, including the ability to communicate with all levels of the organization and participate with multi-functional teams. Qualifications The candidate is expected to have a Master s degree in Industrial & Operations Engineering or related fields, and at least 3 years of work experience. Experience in using tools like Tableau, Power BI, SQL, MRP

Job Details: : In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII. You will be part of ACE Group, in the P-Core design team driving Intels latest CPUs in the latest process technology. Your responsibilities will include but not limited to: Meet the design targets of high performance and low-power digital design.Static timing analysis. Power OptimizationDesign Convergence Experience at IP, SoC level. Ability to work in a highly dynamic environment across geographies. Back end design and implementation of new features. Post silicon performance push activities. PPA improvement and Methodology improvements Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with at least 10 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : You will be part of ACE India , in the P- Core design team driving Intels latest CPUs in the latest process technology. In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in PNR from RTL to GDSII. Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.Static timing analysis.Power Optimization.Design Convergence Experience at IP, SoC level.Ability to work in a highly dynamic environment across geographies.Back end design and implementation of new features.7Post silicon performance push activities. Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 6 or more years of experience in related field or a Bachelors Degree with at least 8 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) . Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting. Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *