The Opportunity Simpplr is looking for a Lead UX/UI designer who excels at user-centric product development to help design the future of work. This is a great opportunity to join a team responsible for a product that is defining the way companies engage and connect with their employees. You ll be working alongside talented and passionate product managers, UX/UI designers, researchers and remotely with members of our engineering team in US, India and the UK - all focused on collectively building a world class application. We bring our A-game every day, and have fun doing it. We are looking for truly awesome, unbelievably talented creators to join us. Your Job Responsibilities What you will be doing: Work through design problems from beginning to end: translating business strategy, research insights, and data into ideas that form disruptive new products and features and improving and simplifying existing workflows. Sketch and prototype ideas to quickly assess viability, and design the workflows and fine - grained details of interactions. Use design thinking to drive cross functional alignment and use storytelling to inspire the team and the organization about the team s vision and problems we are solving. Partner closely with cross - functional (product, engineering, and go to market) teams to regularly ship experiences that drive concrete business outcomes and solve user pain points. Iterate based on feedback from the whole team and your cross - functional partners. Act as a leader and coach within the Product Design team, collaborating with other designers to make their work and the whole team better. Your Skillset What makes you a great fit for the team: Want to be part of creating amazing and innovative experiences that help solve real pain points for our customers while driving concrete metrics and business outcomes and know how to find the right balance. Use data and research to inform your design decisions and are able to assess the impact of your designs with quantitative and qualitative data. Are comfortable operating in a fast paced environment and ambiguous problem spaces Bonus: Worked in the B2B, HR, Productivity space or tackled issues related to communication systems for knowledge workers. Have a track record in using design thinking to drive cross functional alignment and storytelling. Have experience partnering with Product to envision long term product vision, strategy, and roadmap. Bring a strong sense of empathy and a user - centric approach to design. Are excited to work in a positive, supportive environment and want to collaborate as part of a high - caliber, cross - functional team that helps you grow. Have a portfolio showing compelling and quality design as well as a track record of driving design forward. 8 plus years UX/UI Design experience. Simpplr s Hub-Hybrid-Remote Model: At Simpplr we believe that when work is good, life is better and that belief guides all we do. Including how we approach our flexible work model. Simpplr operates with a Hub-Hybrid-Remote model. This model is role-based with exceptions and provides employees with the flexibility that many have told us they want. Hub - 100% work from Simpplr office. Role requires Simpplifier to be in the office full-time. Hybrid - Hybrid work from home and office. Role dictates the ability to work from home, plus benefit from in-person collaboration on a regular basis. Remote - 100% remote. Role can be done anywhere within your country of hire, as long as the requirements of the role are met.

Role & responsibilities : Testing all the incoming Raw materials and the produced finished Goods. Work on ongoing Research work. And report directly to the Director. Sound Knowledge of Basic chemistry principles. Sound Knowledge of lab equipment, titration, isolation, separation & purification Technique Ability to analyze data, Research Oriented and punctual. Positive and confident individuals with strong work ethics. Team player and good communications skills. Experience in Solvent Extraction (SX) will be given top priority. Precise Lab test results needed every time. Should be ready to do R&D work and keep note of the results. Preferred candidate profile Knowledge : BSc (Chemistry),/M.Sc. (Chemistry),/ B. Tech (analytical chemistry, Inorganic Chemistry) Industry Experience Required: Minimum of 3 years Industrial experience as wet chemical analyst in any manufacturing unit. We keep hiring fresher for cultivating in house talent. Perks and benefits :

Title: Memory IP Design Engineer- (eFlash/MTPM/OTP/MRAM/SRAM) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 4-6 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Job Description: Be a member of the team that plays a significant role in ensuring the quality of next generation processors for Smart phones and Smart card through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include Interfacing with the design teams to ensure DFT design rules and guidelines are met. Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. MBIST verification and test pattern generation through Mentor tool. Work closely with design team on IDDQ constrains validation and pattern generation along with IVA analysis. Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and min/max timing corners. Working with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE debug. Lead team of 2-3 engineers working bin DFT/ADFT pattern generation and validation Contribute to technical innovation, development of innovative techniques in the area of test cost reduction, simulation time reduction and quality enhancement Responsible for supporting post Si debug effort, issue resolution Developing, enhancing and maintaining scripts as necessary. Skills: Minimum of 8 -12 year experience in ASIC/DFT and various aspects simulation, Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis. In-depth knowledge and hands on experience in Silicon debug, yield optimization Expertise in test mode timing constraints definition, Hands on experience with prime time is an added advantage Expertise in scripting languages such as perl, shell, etc. is an added advantage Knowledge/experience in post Si debug support Experience in simulating test vectors Working experience in System Verilog, Vera, modelsim tools Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking work on several high priority designs in parallel. Past experience or ability to manage team Excellent problem solving skills Excellent communication and team work skills Experience with test tools such as Tetramax, Logic vision, Modelsim is highly desirable.

Title: Memory IP Design Engineer- (eFlash/MTPM/OTP/MRAM/SRAM) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 4-6 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Individuals who possess skills/experience in one or more of the following are requested to apply: Preferred Qualifications:Areas of Expertise (the more the better): Working experience with Complex Embedded Systems, Mobile/IOT/Auto domains preferred. Expertise in fields such as power / performance use cases , system modeling, SOC Profiling, PPA tradeoffs, post silicon bring up, and product qual. Firm grasp of computer architecture and OS fundamentals Post Silicon System Validation of SOC Performance, Architecture Analysis and Feedback to future products. Analyzing the power-performance data for various CPU, GPU, AI workloads / benchmarks Conducting detailed workload characterization and sensitivity analysis Develop and enhance analysis tools and instrumentation to assist in analysis, identifying performance gaps and optimization options CPU microarchitecture including cache, Latency, BW analysis, etc. Linux/Android kernel development, device driver development and Android architecture experience Collaborate with the architecture team on power-performance trade-off analysis as part of product definition. Power and/or performance optimization, CPU, SOC SW DCVS/DVFS Governors exposure Working experience at System level, Linux kernel internals / system programming Collaborate with internal teams and external partners for analysis and optimizations Lab Hands-on: with Power Data Acquisition/DAQs, Oscilloscope, JTAGs, ARM Developer Studio exposure Exposure to ADB shell, shell scripts, Python scripts, Understanding of Linux/android systems , automation scripts/environment Exposure to Git, Jira, Android and QTI tools Good communication skills, presentation skills and should manage his/her tasks independently Acts as a tech lead on projects and owns the outcome of the project. Advises multiple teams of engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform ARM or DSP based SOC Pre-Si and Post Si validation including system level validation and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Experience in SoC pre/post silicon validation. ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-6yrs experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience : 5 - 8 Years of relevant experience with System level exposure on ARM SOC Mandatory Skills: Good understanding of processor architecture, Multicore/Multiprocessor with SMP/heterogenous cores. Good understanding on Cache hierarchy, coherency, and snoop concepts Good Understanding of CPU Dynamic Frequency and Voltage Switching, Low Power Modes C language expertise for low level programming, Assembly language for any processor. Exposure to CPU Architecture based on ARM or x86. Exposure to SoC architecture paradigms "“ interconnects, power management. Desired Skills Hands on experience On Linux operating system, Kernel debuggers, Kernel and Linux Device drivers Exposure to Memory architecture, through with Weakly ordered memory model and barriers concepts RISC-V architectural knowledge would be an added plus. Exposure to SoC architecture paradigms "“ interconnects, power management. Exposure to working on emulation/pre-si environment is added advantage. Hands on experience with JTAG based debuggers. Bring-up of hardware-software solution on emulation platforms and on fresh SOC designs. ASIC digital design fundamentals and methodology would be an added advantage. Knowledge of Linux kernel internals (process scheduler, memory management, concurrency / synchronization, memory allocation, file systems) and profiling Responsibilities Create the Complex Test content scenarios in the Baremetal/Linux OS world in the process scheduler, memory management, concurrency / synchronization, memory allocation, file systems Able to understand various hardware modules constituting CPU sub-system and its interfaces. Ability to work with hardware design team to develop low level drivers for early enablement. Chalk out hardware functional validation plan, develop test bench and execute during pre and post silicon SOC bring up phases to expose HW issues. Excellent communication skills and ability to work with diverse teams to drive HW debugs to conclusion. Use silicon debug hooks to measure power/performance/coverage and other KPI metrics

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a "CPU Core Validation Engineer" you would be part of CPU Validation team in CPU org working on validation of CPU core pipeline arch and micro arch features. Roles and Responsibilities: Develop detailed test plan considering the IP arch and uarch features. Work with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned. Develop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon. Work with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringup"™s. Minimum Requirements: BA/BS degree in CS/EE with 5+ years"™ experience. 5+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Preferred Requirements: Good understanding of micro-processor architecture, in domains such as:Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness. Experience in writing Test plans and Assembly code. Ability to develop and work independently on a block/unit of the design Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a "SoC Validation Engineer" you would be part of the Automotive SoC Post Silicon Validation Team, within the Automotive SoC team. The charter for SoC Validation Bringup team would be to prepare for and support bring up of every SoC using the Custom CPUs - from first Silicon through to productization. Roles and Responsibilities: Work with different Validation teams to debug and triage SoC issues. Work with SOC bring up teams, software teams to plan debug and triage of SoC. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist debug of SoC. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future debugs. Minimum Requirements: BA/BS degree in CS/EE with 5+ years"™ experience. 3+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools.Preferred Requirements:Strong understanding of micro-processor architecture. Strong understanding of power management, physical design concepts. Experience in Silicon bring up and validation of CPU features. Experience in debug of functional, power, performance and/or physical design issues in silicon. Experience in Test development for validation of CPU features on Silicon. Experience in development of test vectors for tester bring up. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM, System Verilog coding Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Proficiency in any of the Scripting languages (Python or Perl)

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

About The Role : About The Role :: Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. If you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. This job opportunity is in Client Windows system integration & validation team which provides scope to work in a fast paced, leading edge environment with endless possibilities of innovating and learning across Display, Media & 3D domain E2E use-case validation & debug. We strive to lead the industry through continuous innovation and world-class engineering. This is an excellent opportunity to pursue your dream job. As a Graphics Validation Engineer, you will define, develop, and perform platform validation of E2E Graphics usages, focusing on media, display and 3D system level features on Windows. Review functional requirements for test case creation and validation methodologies. Develop & apply various software tools and techniques to ensure validation coverage goals are met as per the specifications. Execute validation plans flawlessly to meet the quality goals. Perform system level debug of failures to identify root causes and collaborate with IP teams for issue fix/resolution. Work with architecture, IP and board teams to maintain and improve validation strategy, debug methodologies for E2E graphics usages and to meet desired product specifications. Job Responsibilities include (but not limited to): Define & develop system level validation plans and strategies to integrate & validate Windows platform Graphics (display, media, 3D) use-cases as per the requirements Work closely with other teams in Architecture, BIOS, Gfx driver, hardware, Firmware & board team to ensure readiness of Graphics use-cases for validation purpose Validate and debug software across the stack for a specific product, platform, windows based Graphics features, or technology Issue triage/debug and faster resolution by collaborating with cross functional IP, Hardware, Firmware, OS and BIOS teams Analyze the results to ensure correct functionality, triages failures, and recommend or develop corrective actions Support Quality events by proactive coordination with relevant stakeholders Effectively collaborate and communicate with global stakeholders Publish Graphics reports summarizing validation results to the relevant teams Assess the state of the art and employ new methods to improve debug, quality Identify opportunities to automate test cases and develop software automation test scripts and utilities Qualifications Job Qualification Candidate should hold BTech/MTech in computer Science or Electronic streams with excellent hold on key engineering subjects Candidate should have 5+ years of relevant experience Strong self-initiative and persistence with ability to deal with ambiguity to focus and achieve end goals. The candidate must have a high focus on discipline in execution, a relentless pursuit of quality and excellent customer orientation. Good debugging and problem-solving skills, comfortable with the use of software and platform tools to diagnose and debug platform Graphics issues Good understanding of Windows Graphics domains namely media, 3D, Display Technologies & E2E platform test case creation and validation. Good knowledge of programming languages like C/C++ or scripting language like Python Must have experience in Window Graphics driver Architecture and its interaction with platform level components Must have excellent written and oral communication skills and be able to effectively collaborate and communicate with global stakeholders. Experience and hands on skills with WinDBG, ITP, Logic Analyzers. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

MTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As a Principal Memory Circuit Design Verification Engineer you will work in a highly innovative, motivated, Upbeat, and dynamic design team capable of verifying complete products using innovative memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally accurate design. Unique Opportunities Complete ownership of verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as HBM,DDR4,LPDDR4,DDR5 and LPDDR5 that can operate at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on multi-functional tasks that can widen your skills. Responsibilities: Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for sophisticated products. Co-work with international colleagues on developing new verification flows to take on the challenges in design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Core Requirements Good communication skills and ability to work well in a team Guide new team members and energetic engineers in the team Analytical capability for complex CMOS and/or gate level circuit designs Proficient with either SPICE and/or Verilog simulations Qualifications & Skills Experience in SystemVerilog, PLI coding, Gate Level Sims Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Bengaluru, Karnataka, India; Hyderabad, Telangana, India Minimum qualifications: Bachelor's Degree in Electrical Or Computer Engineering, or Computer Science, with emphasis on computer architecture, or equivalent practical experience 2 years of experience in Silicon power or performance software development Experience in Linux kernel and device driver development Preferred qualifications: Master's degree in Electrical or Computer Science with emphasis on computer architecture or equivalent practical experience Experience working with cross-functional teams including product management, chip architecture, hardware implementation, and embedded software teams Excellent SoC, Chip System Power Or Performance analysis skills About The Job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Develop software and firmware for Advanced RISC Machine (ARM) Architecture focusing on CPU Power Management Produce detailed documents for the proposed implementation Develop Pre-Silicon and Post-Silicon software development and validate for Power and Performance features Manage Low Power state and Dynamic Voltage and Frequency Scaling (DVFS) management Drive Silicon verification across process, voltage, and temperature Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Bengaluru, Karnataka, India; Hyderabad, Telangana, India Minimum qualifications: Bachelor's Degree in Electrical Or Computer Engineering, or Computer Science, with emphasis on computer architecture, or equivalent practical experience 2 years of experience in Silicon power or performance software development Experience in Linux kernel and device driver development Preferred qualifications: Master's degree in Electrical or Computer Science with emphasis on computer architecture or equivalent practical experience Experience working with cross-functional teams including product management, chip architecture, hardware implementation, and embedded software teams Excellent SoC, Chip System Power Or Performance analysis skills About The Job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Develop software and firmware for Advanced RISC Machine (ARM) Architecture focusing on CPU Power Management Produce detailed documents for the proposed implementation Develop Pre-Silicon and Post-Silicon software development and validate for Power and Performance features Manage Low Power state and Dynamic Voltage and Frequency Scaling (DVFS) management Drive Silicon verification across process, voltage, and temperature Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Minimum qualifications: Bachelors degree in Electrical or Computer Engineering or equivalent practical experience 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture Experience with a coding language like Python or Perl Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience 6 years of industry experience with Internet Protocol (IP) design Experience with methodologies for Register-Transfer Level (RTL) quality checks (e g , Lint, CDC, RDC) Experience with methodologies for low power estimation, timing closure, synthesis About The Job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration In this role, you will design foundation and chassis Internet Protocols (IPs) (e g , Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU) and other peripherals) for Pixel System on a chip (SoCs) You will collaborate with members of architecture, software, verification, power, timing, synthesis etc to specify and deliver a quality Register-Transfer Level (RTL) You will solve technical problems with micro-architecture, low power design methodology and evaluate design options with performance, power and area in mind Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Participate in test planning and coverage analysis Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks Create tools/scripts to automate tasks and track progress Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Project Role : Silicon Firmware & Embedded Engineer Project Role Description : Write the software that powers and operates a silicon chip. Develop pre-silicon firmware and software with a direct interface to hardware. Integrate and develop C tests/APIs and software build flow. Perform design and code reviews. Test and validate product implementations. Must have skills : Embedded C++ Good to have skills : Embedded Hardware Abstraction Layer, No Function Specialty Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Silicon Firmware & Embedded Engineer, you will be responsible for writing the software that powers and operates a silicon chip. Your role involves developing pre-silicon firmware and software with a direct interface to hardware, integrating and developing C tests/APIs and software build flow, performing design and code reviews, and testing and validating product implementations. Roles & Responsibilities: Expected to be an SME. Collaborate and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Provide solutions to problems for their immediate team and across multiple teams. Develop and maintain pre-silicon firmware for silicon chips. Integrate C tests/APIs and software build flow. Conduct design and code reviews. Professional & Technical Skills: Must To Have Skills:Proficiency in Embedded C++. Strong understanding of software development for silicon chips. Experience in developing pre-silicon firmware. Knowledge of hardware-software interface. Hands-on experience with C tests/APIs development. Additional Information: The candidate should have a minimum of 5 years of experience in Embedded C++. This position is based at our Bengaluru office. A 15 years full time education is required. Qualifications 15 years full time education

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for an Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs. What youll be doing: Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices. Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs. IP layout will comprise of significant digital components and some analog components. Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts Follow company procedures and practices for IC layout activities. What we need to see: 2+ years of experience in high performance analog layout in advanced CMOS process. BE/M-Tech in Electrical & Electronics or equivalent experience. Thorough knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required. Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines) Experience with floor planning, block level routing and macro level assembly. Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines. Demonstrated experience with analog layout for silicon chips in mass production. Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred. Experience working in distributed design team is a plus. Requires self-starter with the ability to define and adhere to a schedule. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for an Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs. What youll be doing: Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices. Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs. IP layout will comprise of significant digital components and some analog components. Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts Follow company procedures and practices for IC layout activities. What we need to see: 2+ years of experience in high performance analog layout in advanced CMOS process. BE/M-Tech in Electrical & Electronics or equivalent experience. Thorough knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required. Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines) Experience with floor planning, block level routing and macro level assembly. Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines. Demonstrated experience with analog layout for silicon chips in mass production. Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred. Experience working in distributed design team is a plus. Requires self-starter with the ability to define and adhere to a schedule. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Design analog and mixed-signal modules in CMOS and Power Technologies, with a particular focus on DC-DC converter for power management ICs. In your new role you will: Design analog and mixed-signal modules in CMOS and Power Technologies , with a particular focus on DC-DC converter for power management ICs. Design analog and mixed-signal system resource blocks including POR, Bandgap, LDO, Oscillator, Crystal oscillator and PLL Design precision analog blocks including Amplifiers, DAC and ADC. Assist in defining the requirements for analog and mixed-signal blocks, aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Provide essential support to physical design engineers, post-silicon validation, production testing, and other critical activities extending beyond the design phase. You are best equipped for this task if you have: A Master s Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies Experience in analog and mixed-signal circuit design, particularly in CMOS and Power Technologies Good Analytical skills and very good understanding of Analog Design Familiarity with high-efficiency power conversion, such as DC-DC converters, is highly desirable Experience in post silicon debug Proficiency in computer-aided design tools and methodologies

Knowledge & experience of Microarchitecture, RTL, Synthesis, STA and CDC. Job Description In your new role you will: Defining, designing, and implementing very complex logic blocks. Performing architecture analysis and feasibility for these complex blocks. Working with the SoC lead for full chip implementation from launch to production . Performing RTL design, synthesis and DFT strategy, clocking strategy, validation and verification support. Utilizing industry standards and proprietary tools and methodologies for design, chip integration and design for test. Supporting cross functional teams, including product and test engineering, chip integration, circuit design, verification and validation, in taking SoC into production. Participating in customer design reviews Participate in detailed planning and monitoring to deliver on time milestones. Mentor and develop junior engineers. Your Profile You are best equipped for this task if you have: Education and experience required BS + 12-13 years experience, MS + 10-11 years experience Knowledge & experience of Microarchitecture, RTL, Synthesis, STA and CDC. Experience with Logic Synthesis, Low power, Equivalence, Linting, CDC and DFT tools. Strong written and verbal communication skills are required. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.. Expertise in dealing and designing with complex IPs from different sources onto the same piece of silicon. Expertise in USB / PCIe / micro-controller / USBPD / Power Controller space is an added advantage

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuitblocks , including incorporating features for testing and qualityassurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks , aligning them with IP Module architecture, and ensuringcompliance with requirements through documentation. Estimate effort and planning design work packages to meet projectmilestones. Provide essential support to physical design engineers, post-siliconverification, production testing, and other critical activitiesextending beyond the design phase. You are best equipped for this task if you have: A Master s Degree in Electrical/Electronic Engineering, Physics orequivalent field of studies. Experience in analog and mixed-signal circuit design, particularly inCMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC DCconverters, is highly desirable. Experience in pre-silicon verification and with SystemVerilog wouldbe a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. KEY RESPONSIBILITIES: Verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate-level simulation, power-aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs . ACADEMIC CREDENTIALS: Require BS w/ 6+ yrs or MS w/ 4+ yrs or PhD w/ 2+ yrs in Electrical Engineering, Computer Engineering or Computer Science.