Senior DFT Engineer

Dear Connections,

We are Hiring "DFT Engineers"

• Exp : 3-8 years
• Location : Bangalore/Hyderabad
• Bachelor’s or Master’s in Electrical/Electronics Engineering

Role Summary

We are seeking a skilled Design-for-Test (DFT) Engineer with strong expertise in Scan insertion, ATPG pattern generation, and JTAG/Boundary Scan. The candidate will be responsible for developing and implementing DFT architecture to ensure high test coverage, robust manufacturability, and seamless silicon bring-up.

Key Responsibilities

• Develop and implement DFT architecture for digital ASIC/SoC designs.
• Perform scan insertion, scan stitching, and validation using industry-standard tools.
• Generate high-quality ATPG test patterns for stuck-at, transition, path delay, and compression-based testing.
• Work with JTAG (IEEE 1149.1/1149.6) boundary scan architecture; develop TAP controllers and verify compliance.
• Integrate and verify DFT features (MBIST, LBIST, boundary scan, compression logic).
• Perform DFT verification using simulation and formal methods.
• Drive fault coverage improvements and debug low-coverage areas.
• Support silicon bring-up, tester pattern conversion, and ATE debug (Teradyne/Advantest).
• Collaborate with RTL, physical design, and product engineering teams.
• Create DFT documentation and deliverables (DFT spec, pattern reports, test plans).

Required Skills & Experience

• Strong knowledge of Scan/DFT methodologies, scan insertion, and scan chain verification.
• Hands-on experience with ATPG tools:
• Synopsys TetraMAX / TestMAX
• Cadence Modus
• Mentor/Siemens Tessent
• Solid understanding of JTAG/TAP controller design and boundary scan implementation.
• Experience with Verilog, SystemVerilog, and RTL debug.
• Familiarity with SDC constraints and timing closure for test modes.
• Knowledge of DFT for low-power designs (power domains, isolation, retention).
• Experience with MBIST and/or LBIST is a plus.
• Good understanding of fault models and coverage analysis.
• Strong problem-solving and debugging skills.

Preferred Qualifications

• Experience in ATE pattern bring-up.
• Knowledge of formal verification, STA for DFT modes, and gate-level simulation.

If you are looking for job change share your updated resume to vagdevi@semi-leaf.com

Job Type: Full-time

Pay: Up to ₹3,000,000.00 per year

Experience:

• DFT: 3 years (Required)
• ATPG: 3 years (Required)
• Scan / Jtag: 3 years (Required)

Work Location: In person