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In this role at Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai, you will work directly with a prominent client on next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. **Key Responsibilities:** - Conduct functional verification at both block and chip levels for complex designs - Develop verification test plans based on detailed design specifications - Construct UVM-based simulation environments using System Verilog - Perform coverage analysis to ensure validation completeness - Implement assertion-based verification for functional robustness - Collaborate across teams to align design and verification milestones - Work with RAL to validate register-level behaviors - Create testbenches for simulation - Optimize performance efficiency **Qualifications Required:** - 6 to 10 years of relevant experience in design verification - Proficiency in System Verilog and UVM methodologies - Strong understanding of chip-level verification processes - Ability to develop verification test plans and simulation environments - Experience in coverage analysis and assertion-based verification - Excellent collaboration and communication skills If you are eager to make a significant impact in chip-level verification and advance your career in hardware design, consider applying for this permanent position. Immediate joiners are preferred for this Work from Office opportunity in Siruseri, Chennai. Don't miss the chance to join a dynamic team at Coventine Digital Private Limited and contribute to cutting-edge chip design projects. Send your resume to Venkatesh@coventine.com or contact us directly to explore this exciting career opportunity. Shape the future of hardware design with us!,