807 Rtl Jobs - Page 31

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up

Role & responsibilities : Strong understanding of computer architecture and logic design ->Knowledge of Verilog, system Verilog and UVM is a must ->Strong understanding of state-of-the-art verification techniques, including assertion and constraint-random metric-driven verification ->Define test plans, test benches, and tests using System Verilog and UVM ->Working knowledge of C/C++ and Assembly programming languages ->Exposure to scripting (python preferred) for post-processing and automation ->Experience with gate level simulation, power and reset verification

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Job Responsibilities Responsible for Corporate Application Engineering (CAE) activities in the Design for Test (DFT) Domain of VLSI systems From a technical stand-point, understanding customer needs on DFT, involve and work with their projects for using right methodologies and Siemens tools for successful project completion Provide DFT Tool support to all the existing customers. Help customers improve the productivity through efficient tool usage. Provide onsite tool support to customers as and when needed Developing and delivering technical training on new features and product updates Tracking and updating customer issues using defined Siemens processes and tracking tools. Developing Technical content for Siemens knowledgebase. Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; drive competitive replacements, provide support to customers during critical project implementation phases. Educational qualifications: Required BE/B.Tech in Electronics & Communications Engineering (E&C), or Electrical and Electronics Engineering (EEE) Work Experience: 4+ years relevant experience in DFT area of VLSI domain. Technical skills: In additional to possessing hands-on knowledge of DFT implementation and verification, the position would need excellent problem solving & communication skills able to work independently to solve complex problems and device new solutions and workarounds for customer issues. Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and design for testability. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes ATPG/Scan/Compression based testing, Memory BIST, Logic BIST, IJTAG and Boundary Scan (1149.1/6). Knowledge of scan data compression methodologies with EDT is preferred. Preferred experience in specific areas: Operating SystemsUNIX, Linux, Sun Solaris. LanguagesVerilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++. CAD ToolsSynthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Tessent flows and methodologies is a plus. General/soft skills: Work effectively with customers, internally with divisions and R&D Ability to work autonomously Strong verbal and written communication skills; good presentation skills Excellent organizational and time management skills Build and foster relationships with customer and peers with a positive attitude to win business success Good problem solving and debugging skills, Willingness for technical sales Should be a good team player Job may require some domestic and international travel. #DISW #LI-EDA #LI-Hybrid A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrows reality. Find out more about the Digital world of Siemens here:/digitalminds Siemens Software. Where today meets tomorrow

- Lead the architecture, design and development of Power Management for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Server SoC power management features. * Experience with hardware to model correlation * At least 1 generation of silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Long Description 4. Analog Circuit Design : Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Experience - 7+ Yrs + Lead/Architect Location - Bangalore 5. DFT - ATPG, MBIST Location - Bangalore, Kochi, Pune, Hyderabad Experience - 7 years + DFT Lead Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Understand the design specification , Memory and Memory BIST engine connections Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 4+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 4+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization. ( for SoA) Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking a highly skilled Software Engineer React with 8+ years of experience for an immediate joiner position in Pune or Hyderabad. The role involves designing and developing dynamic, responsive, and high-performance user interfaces using React.js. Responsibilities include building reusable components, managing application state, integrating with backend APIs, ensuring code quality, accessibility, and performance optimization. The candidate will collaborate with cross-functional teams to translate design and business requirements into scalable front-end solutions, while following best practices for testing, version control, and deployment. Experience in banking projects is required.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.You may e-mail or call Qualcomm's toll-free number found . To all Staffing and Recruiting Agencies :

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelors or masters degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include: Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus You may e-mail or call Qualcomm's toll-free number found . To all Staffing and Recruiting Agencies :

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

4+ years of experience in RTL design and verification. Proven experience with digital logic design using Verilog, VHDL, or System Verilog. Experience with simulation tools such as VCS, QuestaSim, or similar. Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus). Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog. Implement complex digital functions and algorithms in RTL. Create and execute detailed test plans to verify RTL designs. Proficiency in writing and debugging RTL code. Experience with synthesis, static timing analysis, and linting tools.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced Debug IP Design Engineer/Microarchitect to focus on the development of Debug IPs. The ideal candidate will have a strong background in IP design, verification, and delivery, with specific expertise in CoreSight IP design. Key Responsibilities: Debug IP Design: Focus on the design and development of CoreSight based Debug IPs, ensuring they meet the required specifications and performance standards. RTL Design: Utilize your experience in RTL design for complex SoC development using Verilog and/or SystemVerilog to create efficient and reliable IPs. Arm-Based Designs: Apply your knowledge of Arm-based designs and/or Arm System Architectures to develop and optimize IPs. Collaboration: Work closely with cross-functional teams, SoC integration & Architecture teams to ensure successful IP delivery within the specified timelines. Quality Assurance: Implement rigorous verification processes to ensure the IPs meet all functional and performance requirements. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Proven experience in RTL design for complex SoC development using Verilog and/or SystemVerilog. Arm Expertise: Strong understanding of Arm-based designs and/or Arm System Architectures. Technical Skills: Proficiency in IP design, verification, and delivery, with a focus on Debug IPs. Communication: Excellent communication and collaboration skills to work effectively with cross-functional teams. Preferred Skills: Experience with CoreSight based Debug IP design. Strong problem-solving and analytical skills Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Job Description Preferred Experienceleading small design team. C coding / Firmware skills Knowledge on common processor architectures(ARM, RiscV) FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA. Lab brings up experience, scripting. Relevant tool experience such as: Socrates, Core Consultant in additionto standard simulation tools (xcellium, vcs, etc) Emulation experience(Zebu, Palladium, etc) Board knowledge, component selection, probing, debug. JTAG debugging experience (Coresight, Lauterbach, etc). Low power design techniques Qualifications E./B.Tech. degree at minimum.

Role & responsibilities Experience : 8+ years in SoC architecture, infrastructure IPs, and system-level integration Employment Type : Full-Time Role Overview We are looking for a highly experienced and technically strong SoC Infrastructure Development Lead to drive design, integration, and verification of infrastructure IPs that form the backbone of our complex SoC platforms. This role requires deep domain knowledge of infrastructure components such as interconnects, clocks, resets, power domains, debug fabric, and system control blocks, and the ability to coordinate across silicon, firmware, verification, and physical design teams. Key Responsibilities SoC Infrastructure Planning and Development Define and drive infrastructure architecture for complex SoCs including clocking, resets, power management, interconnects (e.g., NoC, AXI), system controllers, debug & trace, and eFuse/Fuse ROM . Own the design and development of key infrastructure RTL blocks such as: Global interrupt controllers (GIC), System management units (SMU), QoS managers, Low-power domain controllers (e.g., AOSS, RPMh), Security fuses and OTP handling blocks. Cross-IP Integration & SoC-Level Ownership Drive integration and connectivity of infrastructure IPs with CPU, GPU, memory controller, peripherals, and other functional blocks via NoC or AXI fabrics. Define power domain partitions, reset trees, and clock domain crossings (CDC) at the SoC level. Work with physical design (PD) and architecture teams to optimize floorplan, area, and timing closure for infrastructure-heavy SoCs. Design Enablement & Firmware Interface Collaborate with firmware and bootloader teams to define software-visible control registers (CSR), MMIO maps, and secure/non-secure access policies . Provide clear hardware/software interface (HSI) documentation and support integration of infrastructure blocks into platform bring-up (e.g., LK, UEFI, ATF). Define abstraction layers and APIs for infrastructure management in Linux/RTOS device trees or ACPI tables . Verification and Validation Partner with verification teams to develop test plans, checkers, assertions, and UVM environments for all infra blocks. Drive pre-silicon and post-silicon validation for infrastructure IPs, and help debug corner-case bugs related to interconnects, power, or clocking. Participate in FPGA/emulation/system validation for early firmware bring-up. Required Expertise Technical Skills Strong RTL design skills using Verilog/System Verilog; familiarity with UVM and formal verification flows. In-depth knowledge of AMBA (AXI/AHB/APB), NoC, and coherent interconnects (e.g., CCN, CMN, or NOC from Arteris/NVIDIA) . Expertise in clock tree design , clock gating strategies, and multi-domain reset and power sequencing . Experience with RTL-to-GDSII flows , including timing constraints, SDC generation, and ECO handling. Platform-Specific Expertise Experience working on Qualcomm, ARM, Intel, or custom ASIC platforms , with a solid understanding of SoC assembly and platform integration. Familiarity with: Qualcomm AOSS, RPMh, and RPM message protocol, ARM Coresight & debug/mem-ap infrastructure, Secure boot, eFuse management, and system control registers, DVFS, retention/idle states, and power collapse flows. Tools & Methodologies Proficient with tools like Synopsys Design Compiler, Primetime, VCS, SpyGlass, Questa, or Jasper . Working knowledge of scripts in Python/TCL/Perl for automation of flow and register map generation. Hands-on experience with hardware-software co-validation platforms (e.g., Synopsys ZeBu, Cadence Palladium, FPGA protos) . Soft Skills Strong leadership and mentoring ability across junior RTL/PD/firmware teams. Excellent communication for cross-functional collaboration (architecture, PD, firmware, verification, systems). Structured problem solving, analytical thinking, and SoC-level debug expertise. Preferred Qualifications B.E./B.Tech or M.S. in Electronics, Electrical, or Computer Engineering. Experience leading SoC tape-outs (16nm and below nodes). Exposure to TSMC/Intel/Samsung process techs and PPA tradeoffs. Contributions to open-source SoC architecture or Linux kernel SoC drivers are a plus.

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 15 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure that application requirements are met, overseeing the development process, and providing guidance to team members. You will also engage in problem-solving activities, ensuring that solutions are effectively implemented across multiple teams, while maintaining a focus on quality and efficiency in application design and configuration. Roles & Responsibilities:- Expected to be a Subject Matter Expert with deep knowledge and experience.- Should have influencing and advisory skills.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Expected to provide solutions to problems that apply across multiple teams.- Facilitate knowledge sharing sessions to enhance team capabilities and foster a collaborative environment.- Monitor project progress and provide regular updates to stakeholders, ensuring alignment with project goals.-Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl -Proficient in Unix/Linux environments-Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: -Bachelors degree in computer science, Electronics Engineering or related fields and 12+ years of related professional experience.-Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs- Must Have Skills: Proficiency in Design for Testability (DFT).-Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug- Strong understanding of application architecture and design principles.- Experience with software development methodologies and best practices.- Ability to analyze complex problems and develop effective solutions.- Familiarity with testing frameworks and tools to ensure application quality.-Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Additional Information:- The candidate should have minimum 15 years of experience in Design for Testability (DFT).- This position is based at our Bengaluru office.- A 15 years full time education is required. Qualification 15 years full time education

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space.Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification.Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forwardWork closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA)Tabulate metrics results for analysis comparisonDevelop Place & Route recipes for optimal PPA Minimum Qualifications 7+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute mustComplete ASIC flow with low power, performance and area optimization techniquesExperience with STA using Primetime and/or Tempus is requiredProficient in constraint generation and validationExperience of multiple power domain implementation with complex UPF/CPF definition requiredFormal verification experience (Formality/Conformal)Perl/Tcl, Python, C++ skills are neededStrong problem solving and ASIC development/debugging skillsExperience with CPU micro-architecture and their critical pathLow power implementation techniques experienceHigh speed CPU implementationClock Tree Implementation Techniques for High Speed Design Implementation are requiredExposure to Constraint management tool and Verilog coding experience.

General Summary: Senior/Lead ASIC Verification Engineers with an experience of minimum 5+ yrs Very strong experience with Verilog, System Verilog and UVM Working experience on development of Verification IP of layered protocol High Speed peripheral Interface protocol PCIe Gen4+ onwards, PCIe Experience is a must Strong knowledge on UVM RAL and common register interfaces such as APB, AHB, AXI (ARM), RAM. Working experience on scripting and automation Strong Past experience of developing verification plan from scratch and testbench development using the detailed Specification and TestPlan from the scratch Strong base knowledge on digital design, blocks/components Strong debugging skills and Good knowledge of assertions and functional coverage coding and closure. Good knowledge on code coverage analysis and closure. Good knowledge of any scripting language Strong documentation and presentation skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.You may e-mail or call Qualcomm's toll-free number found .

General Summary: We are seeking a highly skilled and experienced IP Design Engineer to join our dynamic team. The ideal candidate will have a strong background in microarchitecture design, RTL design for complex IPs, and a deep understanding of AMBA or PCIe protocols. This role requires a hands-on approach and a commitment to delivering high-quality, reliable designs. Key Responsibilities: Lead the design and development of ground-up IP solutions, focusing on microarchitecture and RTL design. Collaborate with cross-functional teams to define and implement design specifications and requirements. Ensure the quality and performance of designs through rigorous PLDRC and synthesis processes. Develop and maintain detailed documentation for design processes and methodologies. Troubleshoot and resolve complex design issues, ensuring timely and effective solutions. Stay current with industry trends and best practices in IP design and related technologies. Qualifications: 7-10 years of experience in IP design, with a strong focus on microarchitecture and RTL design for complex IPs. Extensive hands-on experience with AMBA protocol or PCIe protocol. Proficiency in PLDRC and synthesis tools to ensure high-quality design outputs. Strong understanding of digital design principles and methodologies. Experience with design verification and validation processes. Excellent problem-solving skills and the ability to work independently and in a team environment. Strong communication and interpersonal skills. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Preferred Skills: Experience with industry standard design flow tools. Knowledge of ASIC design flows. Familiarity with scripting languages such as Python for automation. Experience with version control systems like Git, clearcase. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Location: Mohali, Punjab Work Shift: Night Shift (MST/PST) Experience Required: 2+ Years Education: Bachelors in IT or Computer Applications related field Job Description: We are hiring experienced Recruiters/Sr. Recruiters to join our dynamic team. This is a hands-on recruitment role focused on sourcing and hiring top-tier talent for cutting-edge technology positions. Key Responsibilities: End-to-end recruitment of core IT roles Engage with candidates through various sourcing channels Screen, interview, and coordinate with hiring managers Maintain strong pipelines and ensure timely closures Key Requirements: Minimum 2 years of IT recruitment experience Strong understanding of deep tech and hardware domains Excellent communication and interpersonal skills Perks & Benefits: Benefits & Perks: 1. Incentives* 2. Monetary Awards* 3. 5-Year Retention Bonus 4. Referral Policy* 5. Internet Reimbursement* 6. Router UPS Reimbursement* 7. Term Life Insurance 8. Accidental Insurance 9. Group Medical Insurance (Family Floater) 10. On-call doctor support 11. Sodexo Benefit 13. Leave Policy 14. NPS - National Pension Scheme 15. LTA Leave Travel allowance. 16. Leave Encashment 17. Bank Assistance 18. Employee's State Insurance* 19. Gratuity 20. Provident Fund 21. Cab facility *Admissibility of the benefit may vary commensurate the department, designation, and role. How to Apply: Send your updated resume to bharti.sharma@spectraforce.com

Location: Mohali, Punjab Work Shift: Night Shift (MST/PST) Experience Required: 2+ Years Education: Bachelors in IT/Engineering or related field Job Description: We are hiring experienced Recruiters/Sr. Recruiters to join our dynamic team. This is a hands-on recruitment role focused on sourcing and hiring top-tier talent for cutting-edge technology positions. Key Responsibilities: End-to-end recruitment for roles in: Computer Vision, Firmware, Embedded Systems SoC, CPU/GPU, ASIC, FPGAs, RTL AR/VR, AI/ML, Deep Learning, Hardware Design Engage with candidates through various sourcing channels Screen, interview, and coordinate with hiring managers Maintain strong pipelines and ensure timely closures Key Requirements: Minimum 2 years of IT recruitment experience Strong understanding of deep tech and hardware domains Excellent communication and interpersonal skills Perks & Benefits: Benefits & Perks: 1. Incentives* 2. Monetary Awards* 3. 5-Year Retention Bonus 4. Referral Policy* 5. Internet Reimbursement* 6. Router UPS Reimbursement* 7. Term Life Insurance 8. Accidental Insurance 9. Group Medical Insurance (Family Floater) 10. On-call doctor support 11. Sodexo Benefit 13. Leave Policy 14. NPS - National Pension Scheme 15. LTA Leave Travel allowance. 16. Leave Encashment 17. Bank Assistance 18. Employee's State Insurance* 19. Gratuity 20. Provident Fund 21. Cab facility *Admissibility of the benefit may vary commensurate the department, designation, and role. How to Apply: Send your updated resume to kirti.rapta@spectraforce.com

DV Manager: 12+ Years Location: Bangalore Notice: 0 - 15 Days Summary Senior technical leadership position responsible for ASIC/RTL design verification, team management, and implementation of verification strategies using advanced tools and methodologies. Key ResponsibilitiesResponsibilities 1 Lead and manage verification team of 10+ members (Must have) 2 Develop and implement verification strategies using System Verilog 3 Oversee OVM/UVM implementation and verification processes 4 Manage simulation environments across multiple platforms (Synopsys/Mentor Graphics/Cadence) 5 Drive scripting and automation initiatives 6 Lead debugging and analysis of complex digital design issues 7 Oversee verification of processor subsystems 8 Manage validation suite creation and automation 9 Guide silicon bring up and testing processes 10 Ensure quality and completeness of verification deliverables Qualifications & SkillsEducation B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering Experience 12+ years in ASIC/RTL design verification Skills: System Verilog Testbench Architecture, OVM, UVM expertise, Simulator tools (Synopsys/Mentor Graphics/Cadence), Scripting languages (Perl, Python, Shell, Tcl/Tk), Hardware verification languages (SystemVerilog, SystemC), Hardware description languages (Verilog, VHDL), AMBA, AHB, AXI, JTAG protocols, Gate-Level Simulation and Debugging, Processor subsystems (ARM/RISC), Silicon testing and bench application. Contact: 91 97041 22348 / hr@singhtechservices.com

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12-16 yearsof experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take initiatives. Highly motivated team player with exceptional leadership capability. Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications. Design and implement simulation environments and testbenches to validate FPGA functionality and performance. Create and run functional and directed/random test scenarios to ensure comprehensive design coverage. Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage. Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle. Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality. Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

A Design Verification Engineer (DVE) is responsible for ensuring the functionality and reliability of electronic designs through rigorous testing and validation. They work closely with design teams to develop and execute comprehensive verification plans, identify and resolve design flaws, and ensure compliance with industry standards and specifications. Essentially, they act as the gatekeepers of quality for new products, ensuring they meet performance and reliability goals before release. Key Responsibilities: Developing and Executing Verification Plans: DVEs create detailed test plans, testbenches, and verification components to thoroughly test digital designs. Collaborating with Design Teams: They work closely with logic designers, architects, and other stakeholders to understand design specifications and requirements. Using Simulation and Analysis Tools: DVEs utilize various simulation and analysis tools to validate designs and identify potential issues. Troubleshooting and Debugging: They analyze failing tests, identify root causes of design flaws, and work with design teams to implement solutions. Ensuring Compliance: DVEs verify that designs meet all relevant industry standards, regulations, and performance requirements. Documenting Verification Activities: They maintain detailed records of verification plans, test results, and identified issues. Staying Up-to-Date: DVEs keep abreast of the latest verification methodologies, tools, and technologies. Participating in Design Reviews: They contribute to design reviews, offering insights and feedback to improve the overall quality of the design. Required Skills and Qualifications: Hardware Description Languages (HDLs): Proficiency in languages like Verilog, VHDL, or SystemVerilog is essential. Verification Methodologies: Knowledge of methodologies like UVM (Universal Verification Methodology) is crucial for developing sophisticated testbenches. Simulation Tools: Familiarity with industry-standard simulation tools (e.g., ModelSim, VCS, Verdi) is required. Scripting Languages: Experience with scripting languages like Python or Perl is often needed for automation and test environment development. Problem-Solving Skills: DVEs need strong analytical and troubleshooting skills to identify and resolve complex design issues. Communication Skills: Effective communication is vital for collaborating with design teams and presenting findings. Education: A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is typically required.