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ASIC RTL Integration Manager, Silicon

ASIC RTL Integration Manager, Silicon

Google

15 - 20 years

10 - 14 Lacs

Bengaluru

Posted:1 day ago| Platform:

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Skills Required

Electrical engineering ASIC DFT Coding Chip design Verilog atpg Silicon RTL Physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Minimum qualifications:

Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
15 years of experience in ASIC RTL design integration.
Experience in Verilog or Systemverilog coding.
Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon.

Preferred qualifications:

Master s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software.
Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Lead a team of ASIC RTL engineers on Sub-system and chip-level Integration activities including planning tasks, hold code and design reviews, code development of features.
Interact closely with architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for Sub-system/chip-level integration.
Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

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ASIC RTL Integration Manager, Silicon