RTL Engineer

Role Overview: You will be a mid-level RTL Engineer at saasgenie, where you will be responsible for building and curating high-quality RTL datasets for AI training and evaluation. Your primary tasks will involve reviewing, labeling, and generating Verilog/SystemVerilog designs, bug/fix pairs, and testable modules. Key Responsibilities: - Write, review, and annotate Verilog/SystemVerilog code for training and evaluation datasets. - Generate and validate parameterized RTL designs such as FIFOs, ALUs, and interconnects. - Identify and document common RTL bugs and fixes for supervised learning. - Collaborate with AI engineers to evaluate LLM-generated RTL code. - Maintain quality metrics on correctness, synthesisability, and code coverage. Qualifications Required: - 4+ years of experience in RTL design using SystemVerilog/Verilog. - Strong understanding of synthesis, linting, timing, and design-for-verification practices. - Experience with at least one full chip or IP-level tape-out. - Familiarity with tools like Yosys, Verilator, Synopsys DC, or Cadence Genus is preferred. - Passion for automation, data-driven workflows, and next-generation EDA. - Proficiency in Python and general data analytics skills/data annotation experience are added advantages. At saasgenie, you will become part of a vibrant team where your contributions are valued immensely and directly fuel collective success. The culture thrives on integrity, trust, respect, and collaboration, celebrating flexibility, quick learning, and an achiever mindset. Every individual is empowered to excel, ensuring well-being is always at the forefront. saasgenie provides an ecosystem where you can make a real impact and grow both personally and professionally.,