9 Cadence Genus Jobs

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwid...

Role Overview: You will be a mid-level RTL Engineer at saasgenie, where you will be responsible for building and curating high-quality RTL datasets for AI training and evaluation. Your primary tasks will involve reviewing, labeling, and generating Verilog/SystemVerilog designs, bug/fix pairs, and testable modules. Key Responsibilities: - Write, review, and annotate Verilog/SystemVerilog code for training and evaluation datasets. - Generate and validate parameterized RTL designs such as FIFOs, ALUs, and interconnects. - Identify and document common RTL bugs and fixes for supervised learning. - Collaborate with AI engineers to evaluate LLM-generated RTL code. - Maintain quality metrics on corr...

We are seeking a skilled and enthusiastic Digital Physical Design Engineer (G2) to contribute to the physical implementation of complex digital integrated circuits. This role involves working on various stages of the physical design flow, from synthesis to tape-out, ensuring performance, power, and area targets are met. Job Responsibilities * Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). * Perform physical verification (DRC, LVS, Antenna) and resolve related issues. * Conduct power integrity analysis (IR drop, EM) and optimize designs for power efficiency. * Participate in design-for-test (...

As an experienced RTL designer, you will be responsible for working on complex high-performance RTL design, with a focus on DSP or processor-based sub-systems. Your expertise in hardware design using Verilog, System Verilog, or VHDL, along with knowledge of on-chip bus interface protocols such as AXI, APB, and AHB, will be essential for success in this role. Additionally, your experience with model development, RTL to gate synthesis, design rule checking, and scripting languages will be valuable assets. Key Responsibilities: - Develop micro-architecture, design, and program specific documentation - Design and model compute ASIC modules and sub-systems - Own RTL development, ensuring power, p...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) The Role The position will involve w...

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow s...

Qualcomm India Private Limited is seeking a Hardware Engineer with expertise in complex high-performance RTL design, particularly on DSP or processor based sub-systems. You should be proficient in hardware design using Verilog, System Verilog, or VHDL and have knowledge of on-chip bus interface protocols like AXI, APB, and AHB. Experience in model development (SystemC, or C++), RTL to gates synthesis (Synopsys DCG or Cadence Genus), design rule and CDC checking (SVA assertions, Spyglass, 0-in), and working on high-performance low power RTL design is essential. Familiarity with scripting languages such as PERL, Python, TCL, C, etc., is also required. As a Hardware Engineer at Qualcomm, your r...

4+ years of experience in RTL design and verification. Proven experience with digital logic design using Verilog, VHDL, or System Verilog. Experience with simulation tools such as VCS, QuestaSim, or similar. Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus). Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog. Implement complex digital functions and algorithms in RTL. Create and execute detailed test plans to verify RTL designs. Proficiency in writing and debugging RTL code. Experience with synthesis, static timing analysis, and linting tools.

4+ years of experience in RTL design and verification. Proven experience with digital logic design using Verilog, VHDL, or System Verilog. Experience with simulation tools such as VCS, QuestaSim, or similar. Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus). Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog. Implement complex digital functions and algorithms in RTL. Create and execute detailed test plans to verify RTL designs. Proficiency in writing and debugging RTL code. Experience with synthesis, static timing analysis, and linting tools.