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RTL Engineer saasgenie

4.0 - 8.0 years

0 Lacs

chennai, tamil nadu

On-site

Role Overview: You will be a mid-level RTL Engineer at saasgenie, where you will be responsible for building and curating high-quality RTL datasets for AI training and evaluation. Your primary tasks will involve reviewing, labeling, and generating Verilog/SystemVerilog designs, bug/fix pairs, and testable modules. Key Responsibilities: - Write, review, and annotate Verilog/SystemVerilog code for training and evaluation datasets. - Generate and validate parameterized RTL designs such as FIFOs, ALUs, and interconnects. - Identify and document common RTL bugs and fixes for supervised learning. - Collaborate with AI engineers to evaluate LLM-generated RTL code. - Maintain quality metrics on corr...

Posted 3 days ago

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