4.0 - 8.0 years

0 Lacs

chennai, tamil nadu

On-site

Role Overview: You will be a mid-level RTL Engineer at saasgenie, where you will be responsible for building and curating high-quality RTL datasets for AI training and evaluation. Your primary tasks will involve reviewing, labeling, and generating Verilog/SystemVerilog designs, bug/fix pairs, and testable modules. Key Responsibilities: - Write, review, and annotate Verilog/SystemVerilog code for training and evaluation datasets. - Generate and validate parameterized RTL designs such as FIFOs, ALUs, and interconnects. - Identify and document common RTL bugs and fixes for supervised learning. - Collaborate with AI engineers to evaluate LLM-generated RTL code. - Maintain quality metrics on corr...

Posted 2 weeks ago

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RTL Design Lead / Manager BITSILICA

8.0 - 12.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced RTL Design Lead, you will be responsible for driving the architecture, micro-architecture, and RTL development of digital IP/SoC blocks. Your key responsibilities will include: - Leading RTL design activities for complex IPs or SoC sub-systems. - Working closely with architects to translate high-level specifications into micro-architecture and RTL. - Driving design reviews, coding standards, and technical quality. - Defining and implementing RTL design methodologies and flows. - Collaborating with verification, DFT, synthesis, and backend teams to ensure successful integration and tapeout. - Guiding and mentoring junior designers in the team. - Supporting silicon bring-up a...

Posted 1 month ago

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Senior RTL Design Engineer DSP/ASIC/FPGA Talenton Technology Services

8.0 - 13.0 years

40 - 80 Lacs

bengaluru

Work from Office

Senior RTL Design Engineer DSP / ASIC / FPGA Experience: 10 to 15 years Location: Bangalore (On-site) Employment Type: Full-time / Permanent About the Role We are seeking a highly skilled Senior RTL Design Engineer to join our digital design team. The selected candidate will be responsible for the RTL design and development of signal processing pipelines for high-performance ASIC and FPGA-based SoCs. Key Responsibilities Develop and integrate custom sub-components of the digital signal processing pipeline such as filters, FFTs, control logic, etc. Write micro-architecture specifications, code RTL, and perform verification and validation of DSP components. Optimize RTL for performance, area, ...

Posted 1 month ago

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RTL Design Lead / Manager BITSILICA

8.0 - 12.0 years

0 Lacs

hyderabad, telangana

On-site

You are a highly experienced RTL Design Lead responsible for driving the architecture, micro-architecture, and RTL development of digital IP/SoC blocks. Your role involves leading RTL design activities for complex IPs or SoC sub-systems and collaborating with various teams to ensure successful integration and tapeout. You will be required to mentor junior designers, support silicon bring-up, and debug as needed. To excel in this role, you must have a proven track record of delivering IP or SoC designs from spec to GDSII. Your expertise should include micro-architecture development, pipelining, clock-domain crossing, and a good understanding of the ASIC design flow. Hands-on experience with A...

Posted 3 months ago

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Manager ASIC RTL Engineer / Digital Design Praxis Hr Solution

6.0 - 11.0 years

12 - 22 Lacs

Kochi, Hyderabad, Pune

Hybrid

Role : ASIC RTL Engineer / Digital Design Location . pan India or Onsite. SoC subsystem/IP design, RTL quality checks (Lint, CDC) If you interested so please share your updated cv at sugrabano@praxists.co.in - 9582126775

Posted 4 months ago

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