NoC Verification Engineer

NoC Verification Engineer

Experience

Key Responsibilities:

🔸Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.

🔸Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.

🔸Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe connected via NoC.

🔸Model and validate credit-based flow control, packet routing, QoS, and virtual channel behavior.

🔸Perform assertion-based verification (SVA/DVL) for protocol compliance and corner cases.

🔸Debug complex interactions at simulation or emulation level, including deadlocks, congestion, or ordering violations.

🔸Work closely with architects and RTL teams to align verification coverage and performance metrics.

🔸Perform coverage closure (code + functional) and ensure complete verification sign-off.

Required Skills:

🔸Strong experience with SystemVerilog, UVM, and object-oriented testbench development.

🔸In-depth knowledge of NoC protocols (AXI4, CHI, TileLink, or proprietary NoC).

🔸Verification experience with coherent interconnects, cacheable traffic, and memory subsystem validation.

🔸Familiarity with Synopsys, Cadence, or Siemens verification tools (VCS/Xcelium/Questa).

🔸Familiarity with formal verification, assertions (SVA/PSL), and coverage metrics.

🔸Ability to debug low-level issues using waveform analysis, scoreboards, and transactors.

🔸Familiarity with multi-core CPU, DSP, or GPU interconnect systems is a plus.

Location: Bangalore

About Company:

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.