Memory Layout Engineer

Chip Smart Technologies Pvt Ltd

0 years

0 Lacs

noida uttar pradesh india

Posted:1 day ago| Platform:

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Skills Required

layout design optimization technology writing test simulation extraction lvs drc debugging cadence scripting automation compiler power constraints resolve electrical engineering

Work Mode

On-site

Job Type

Full Time

Job Description

Industry experience in Memory Leafcell layout design
Strong understanding of memory architectures and performance optimizationStrong grasp of FinFET technologyHands-on experience in memory domain: characterization, design, and validationProficient in writing Spice decks, stimulus, and test vectorsExperience with fast simulation tools and waveform vowereKriowledge of layout parasitic extraction and deep submicron technology challengesGood at LVS/DRC debugging skills and other verifications for lower technology nodesFamiliar with EDA tools like Cadence SKILL scripting and automation for compiler Rows and layout reuseFamiliarity with NMDL + CCST librariesUnderstanding layout effects on the circult such as speed, capacitance, power and area etc..Capable of generating libs and performing QA sign-offAbility to understand design constraints and implement high-quality layouts.Good people siills and critical thinking abilities to resolve the issue technically, and professionally.Minimum Educational Qualification: Educational Bachelor's, Electrical or Electronics Engineering or equivalent Rennirements

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Memory Layout Engineer