Lead Physical Design Engineer – PnR / STA/RTL/Netlist To GDSII

8 - 13 years

15 - 25 Lacs

Posted:5 hours ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

We are looking for an experienced Lead Physical Design Engineer (PnR/STA) to drive end-to-end physical implementation activities from RTL/Netlist to GDSII. The ideal candidate will take ownership of complex blocks/SoCs, lead teams, and ensure high-quality silicon delivery across advanced technology nodes.

Key Responsibilities

  • Lead end-to-end Physical Design flow from RTL/Netlist to GDSII
  • Ownership of PnR, STA, CTS, and Synthesis for blocks and top-level designs
  • Develop, review, and maintain SDC constraints across design stages
  • Perform timing analysis (setup, hold, OCV, AOCV, POCV) and timing closure
  • Drive Clock Tree Synthesis (CTS) and resolve clock-related challenges
  • Ensure clean sign-off for timing, power, and physical checks
  • Handle PV checks including DRC, LVS, ERC, and Antenna
  • Support tape-outs, manage last-minute ECOs, and ensure schedule adherence
  • Collaborate with RTL, DV, DFT, and Foundry teams for seamless integration
  • Mentor junior engineers and provide technical leadership to the team
  • Participate in design reviews, risk assessment, and project planning

Key Expertise / Skills

  • Strong hands-on experience in RTL/Netlist to GDSII flow
  • Expertise in Physical Design, PnR, STA, Synthesis, and CTS
  • In-depth knowledge of Timing Analysis and SDC constraints
  • Experience with sign-off methodologies and successful tape-outs
  • Solid understanding of physical verification (PV) checks
  • Proficiency with industry-standard EDA tools (Synopsys/Cadence)
  • Experience working on advanced technology nodes (preferred)
  • Strong debugging, problem-solving, and decision-making skills
  • Leadership & Collaboration
  • Proven ability to lead and guide teams (24 years)
  • Effective stakeholder management and cross-functional coordination

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