615 Design Verification Jobs - Page 19

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areasinstruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 15+ years of Hardware Engineering or related work experience. 4+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF). 4+ years of experience utilizing schematic capture and circuit stimulation software. 4+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 4+ years in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages expert Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Drives the development of design rules and processes for electronic hardware, equipment, and/or integrated circuitry. Serves as an expert resource for conducting highly complex simulations and analyses of designs as well as for the implementation of designs with the best power, performance, and area. Collaborates with high-level representatives across functions (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement and drive new requirements and the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing solutions for leading edge products in highly advanced processes and bring-up product to meet customer expectations and schedules. Serves as an expert resource for the evaluation of reliability for highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Advises multiple teams of engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues. Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for experienced engineers. Level of Responsibility: Provides supervision to direct reports. Decision-making is critical in nature and highly impacts program, product, or project success. Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents. Works within the prescribed budgetary objectives of the department. Has a great degree of influence over key organizational decisions. Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Expertise in AMBA protocols (CHI/AXI/AHB) Excellent analytical skills, should have an experience of leading a team of 7-8 engineers Knowledge of ARM architecture be an added advantage Exposure to low power methodology with understanding of UPF Handson experience of GLS and timing simulations Exposure to Formal verification Self-driven and motivated to work in a high pressure environment Good at stakeholder management with good communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Details: Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in electrical engineering or computer engineering with 4 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 3+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Monitoring and improve existing simulation environments and simulation efficiency. Experience with Debugging and ACM domain will be a plus. Job TypeExperienced Hire ShiftShift 1 (India) Primary Location India, Bangalore Additional Locations Business groupThe Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Verification and Validation R&D Primary responsibilities: Represent the Design Quality function on device development project teams and cross functional co-ordination with multiple departments including R&D, Quality Control, Manufacturing and Regulatory Affairs. Ensure that device development projects and changes to existing devices are conducted in compliance with the FDA 21CFR Part 820 Quality System Regulation, ISO 13485 Regulations, and other applicable standards like ISO 14971. Provide input to design and manufacturing documentation including material specifications, drawings, inspection procedures, and manufacturing procedures, to ensure that the resulting devices can be adequately manufactured and verified. Lead or support design activities including design verification, validation, test procedure development, usability engineering, and risk management. Generate or apply statistical methods with appropriate risk-based justification. Hands-on experience in Design History File compilation / Technical file documentation. Support internal and external inspections/ regulatory audits. Promote continuous improvement in design control activities and use of quality tools with design team. In-depth knowledge and understanding of 21 CFR Part 820 Quality System Regulation, ISO 13485 Quality Standard, 21 CFR 4 Regulation of Combination Products, 14971 Risk Management Standard, MDD, MDR, IEC/EN 62366 Application of Usability Engineering to Medical Devices, and ANSI HE75 Human Factors Engineering in Design of Medical Devices Secondary responsibilities (Wherever applicable): Experience interacting with regulatory agencies and notified bodies Experience with process improvements, process qualification and validation. Experience in complaint investigation, corrective action and preventive action system, statistical methods, quality risk management and Post Market Surveillance.

Role & responsibilities Job description We are seeking a detail-oriented hardware design engineer for design and development activities of our product line (SMPS/Chargers etc). The following would be the main responsibilities: 1. Hands on Experience on, SMPS & Chargers. 2. Knowledge of Power electronics. 3. Hands on Experience in circuit design, simulation, filter design, schematic & Layout, Micorcontroller based designs, UART/RS232/RS485/CAN/ LIN communication, DFMEA. 5. Hands on experience in validation jig designing using arduino. 6. Knowledge of transformers and inductors calculation, Thermal calculations and components selections/design, BOM preparation. 7. Knowledge of power switching topologies. like fkyback, LLC, PFc topologies. 8. Special Preference who has experience in, Inverters design & charger designing etc.. 9. Hands on Experience in Design Verification and Product Validation. 10. Good understanding on EMI/EMC, ESD testing. 11. Resolve issues in mass production of the design and manufacturing assembly line. 12. Go-Getter, Self Learner, Positive Attitude Preferred candidate profile Only Male Candidate, Willing to work in 6 days working setup. Perks and benefits Insurance,Bouns ,PF

Technical knowledge Design of sensor/ transducer interface and signal conditioning circuits, motor control driver circuits, DC- DC converters, selection of micro controllers as per system requirement, micro controller interface design etc., Development of analog and microcontroller-based control modules and systems. Design verification and testing for conformance to EMI/ EMC and various regulatory standards Design of analog/ digital and mixed circuit design, circuit simulation and analysis needed for development of control and display board for laboratory and industrial machine control. Should have executed similar development tasks right from initial conceptual stage through system engineering till prototype verification and acceptance. Knowledge of statutory testing and verification of the product through testing and evaluation such as CE compliance and similar standards. Preparation of test plans, specifications document, preparing and maintaining project schedules are part of essential qualifications. Knowledge of DFMECA, reliability prediction and design verification and standardization preferred. Leadership Must be technically sound. Guiding a team of young hardware engineers to achieve the goal. Ability to identify and source the right controllers and components for reliable and cost effective design which will meet customer requirement. Good at Planning and execution and estimation various task involved in electronic product/ module development. Ability to plan the infrastructure such as setting of testing lab including test instruments needed. Ability to make good technical proposal Ability of sustain team spirit. Design knowledge to take care of EMI/ EMC and other regulatory requirement as per industrial and automotive standards. Setting up a good design process by preparing and maintaining design guidelines and checklists.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Hardware debug skills backed by relevant experience on projects Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , etc Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Expertise in logic synthesis, conformal, static timing analysis and Place and Route (PnR) Hands on experience in all aspects of the chip development process Experience in creating or improving low power synthesis methodologies Experience with scripting languages like Perl, Tcl or Python Floorplan, Place and Route at block level, physical design verification, LVS, DRC, IR drop analysis; netlist to gds at block level RTL logic design or implementation experience on multi-million gate ASICs will be a plus Strong communication skills to effectively communicate across all internal groups Description: As a synthesis, PnR Engineer, you will have responsibilities spanning various aspects of SOC design and implementation. Responsible for activities like Synthesis, LEC, Conformal, P&R etc. You will be working closely on methodology for improving synthesis QOR. Responsible for floor planning, placement and routing at block level. Will need to work closely with other engineers that are members of the RTL, STA and Physical Design teams. Education & Experience: BS or MS in EE, EECS, or CS is required 4+ years relevant work experience

3+ years of experience in IP/SOC verification Strong expertise in DDR protocols Hands-on experience with verification methodologies (UVM, System Verilog.)

Lead /Senior Design Verification Engineer-GLS/UVM |Hyderabad, India | Experience:7-12 Years Role Overview: We are looking for an experienced and detail-oriented Design Verification Engineer with strong expertise in Gate-Level Simulation (GLS) and SystemVerilog/UVM methodology . The role involves validating complex SoC/IP designs in post-synthesis environments, working closely with design, DFT, and physical implementation teams. Experience with HBM (High Bandwidth Memory) is a strong advantage. Key Responsibilities: Develop and maintain UVM-based verification environments for complex digital IP and SoCs. Plan and execute GLS (Gate-Level Simulation) flows including SDF annotation, X-checking, and timing-aware validation. Perform debug of timing-related and X-propagation issues at netlist level. Drive regression automation, simulation coverage analysis, and documentation of results. Work closely with cross-functional teams (DFT, synthesis, STA, PD) to resolve post-synthesis and post-layout issues. (Optional) Support validation of HBM interfaces , including protocol-level behavior and error scenarios. Required Skills: 7-12 years of design verification experience in ASIC or SoC environments. Solid expertise in SystemVerilog, UVM , and assertion-based verification. Strong hands-on experience in GLS including: SDF annotation Debugging setup/hold, X issues Power-aware simulations (optional) Familiarity with simulation tools : VCS, Xcelium, Questa, Debussy/Verdi. Experience with scripting (Perl, Python, Shell) for automation. Good understanding of chip lifecycle from RTL to GDSII. Nice to Have: Experience working with HBM protocols or memory controller verification. Exposure to low-power verification , UPF flows. Familiarity with post-silicon bring-up and debug is a plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Position #1: Lead/Senior Design Verification Engineer - CPU / RISC-V Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | RISC-V | CPU Subsystems Role Overview: We are seeking an experienced Design Verification (DV) Engineer to join our core CPU verification team focused on RISC-V based processors and subsystems . This is a hands-on role requiring strong technical knowledge in processor architecture , microarchitecture verification , and end-to-end validation of complex SoCs. Key Responsibilities: Develop and execute test plans and environments for CPU and RISC-V based subsystems. Build UVM-based verification environments for simulation and regression. Create testbenches, assertions, checkers, and functional coverage models. Debug failures using waveform viewers, logs, and deep architectural understanding. Collaborate with architects, designers, and firmware teams across all verification phases. Required Skills: 612 years of hands-on DV experience, primarily on CPU cores or RISC-V . Strong understanding of RISC-V or ARM microarchitectures . Proficient in SystemVerilog, UVM , and scripting (Python/Perl/Tcl). Experience with cache coherency, MMUs, branch prediction, or pipeline logic is a plus. Exposure to verification tools like VCS, Questa, or Xcelium . Position #2: Lead/Senior Design Verification Engineer - High-Speed PCIe Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | High-Speed Interfaces | PCIe Gen4/Gen5 Role Overview: We are looking for a skilled Design Verification Engineer with expertise in high-speed interface protocols , particularly PCI Express (PCIe) . The role will focus on validating complex SerDes-based subsystems and ensuring full compliance and performance coverage. Key Responsibilities: Define and implement UVM-based testbenches for PCIe-based subsystems. Verify protocol-level compliance (PCIe Gen4/Gen5/Gen6). Generate, run, and debug simulations across various protocol scenarios and stress conditions. Ensure full coverage functional, code, and assertion-based . Collaborate with silicon validation and firmware teams for end-to-end test alignment. Required Skills: 612 years of DV experience with PCIe (mandatory) and high-speed interface protocols. Strong command of UVM, SystemVerilog , and assertion-based verification. Deep understanding of PCIe layers , packet formats, credit flow, and link training. Experience with VIPs (Synopsys/Cadence/Mentor) and waveform debugging tools. Knowledge of AXI/AMBA , DDR, or USB is a strong plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Key member of design verification team, which has both mixed-signal and digital design verification engineers. The candidate will be responsible for formulating verification strategies and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both INA and ADI. It is expected that he/she will be able to understand and influence other disciplines (analog/digital design) to achieve better all-round chip verification. The candidate is also encouraged to participate in cross company technical initiatives as we'll as patent and publish work where possible Requirements B.Tech/M.Tech with 8+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of analog/mixed-signal building blocks such as power management, ADCs, DACs, PLL, bandgap references, oscillators etc and related digital control and signal processing Demonstrated experience of verification plan, verification environment development and verification/debug of complex mixed signal products at chip-top level Experience of co-simulations with analog model/transistor level and digital RTL/Gate+SDFs, experience of circuit simulations with Spice/Fast Spice simulators Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe Responsibilities Come up with verification strategy for a product after going through product requirements and design specifications Interact with digital/analog leads to get agreement on verification strategy Create models for analog/mixed-signal blocks for chip-top verification, tradeoff accuracy Vs speed. Validate models against actual design (self-checking tests) Create verification plans, build verification environment, develop self-checking testcases. Bring up chip top mixed-signal verification environments (AMS and DMS DV environments) Deploy industry standard SV/UVM based metric driven verification approach Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc) for first pass silicon Support test and characterization teams in post-silicon validation Collaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM, mentor junior DV engineers in the team Skill Set [Experience of following is desired, not all but most of them] Modelling of analog blocks - SV-RNM - Verilog-AMS - Schematic based structural models (macro models) - System C Familiarity with analog/mixed-signal design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision Chip-top co-simulation with tools such as Cadence ADE/Cadence AMSD with Spectre as the analog solver and Xcelium as the digital solver Experience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS Experience with Spice/Fast Spice simulators such as Spectre Ultrasim/APS/XPS Experience with SV/UVM (agent creation, env building, score-boarding, RAL etc) Experience with third-party IP integration Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager Experience with languages/tools/software relating to product development is an added advantage - C, C++, System C, AMS - Automation with scripting languages: Python/Perl/Shell etc - Embedded programming for on-chip micros or separate MCUs - Matlab/Simulink for system level simulations and modeling

Job Information Job Opening ID ZR_2074_JOB Date Opened 06/12/2023 Industry Technology Job Type Work Experience 8-12 years Job Title Lead Hardware Engineer City Coimbatore Province Tamil Nadu Country India Postal Code 641001 Number of Positions 4 Technical knowledge Design of sensor/ transducer interface and signal conditioning circuits, motor control driver circuits, DC- DC converters, selection of micro controllers as per system requirement, micro controller interface design etc., Development of analog and microcontroller-based control modules and systems. Design verification and testing for conformance to EMI/ EMC and various regulatory standards Design of analog/ digital and mixed circuit design, circuit simulation and analysis needed for development of control and display board for laboratory and industrial machine control. Should have executed similar development tasks right from initial conceptual stage through system engineering till prototype verification and acceptance. Knowledge of statutory testing and verification of the product through testing and evaluation such as CE compliance and similar standards. Preparation of test plans, specifications document, preparing and maintaining project schedules are part of essential qualifications. Knowledge of DFMECA, reliability prediction and design verification and standardization preferred.LeadershipMust be technically sound. Guiding a team of young hardware engineers to achieve the goal. Ability to identify and source the right controllers and components for reliable and cost effective design which will meet customer requirement. Good at Planning and execution and estimation various task involved in electronic product/ module development. Ability to plan the infrastructure such as setting of testing lab including test instruments needed. Ability to make good technical proposal Ability of sustain team spirit. Design knowledge to take care of EMI/ EMC and other regulatory requirement as per industrial and automotive standards. Setting up a good design process by preparing and maintaining design guidelines and checklists. check(event) ; career-website-detail-template-2 => apply(record.id,meta)" mousedown="lyte-button => check(event)" final-style="background-color:#2B39C2;border-color:#2B39C2;color:white;" final-class="lyte-button lyteBackgroundColorBtn lyteSuccess" lyte-rendered=""> I'm interested

Design engineers Fresher are responsible for the design, development, and testing of products and components across a variety of industries. Software - AutoCAD, Solid work Walking Interview Location - Chakan, Pune Contact - Maya 9767897450

nikita.chaudhary@enlink.com Job Title: Design Verification Engineer SoC/IP Verification Location: Bangalore Job Type: [Full-Time] Experience : 5 to 9 Years Job Description: We are looking for experienced Design Verification Engineers with a strong background in SoC and IP-level verification. The ideal candidate will be responsible for developing and implementing advanced verification environments and ensuring the functional correctness of complex digital designs. Key Responsibilities: Develop and maintain verification environments for SoC and IP designs Implement test bench components and verification infrastructure Create and execute test cases to ensure thorough validation of designs Develop and track functional coverage metrics Write and integrate assertions for design verification Perform failure analysis and debug issues efficiently Work with high-speed interface protocols such as PCIe Gen6, CXL,Ethernet, and UCIe Required Skills: Strong experience in SystemVerilog/UVM-based verification methodologies Solid understanding of digital design and verification flows Proven skills in debugging and failure analysis Experience with functional coverage and assertions Hands-on experience with at least one of the following protocols:PCIe Gen6, CXL, Ethernet, or UCIe Excellent communication and teamwork skills Preferred Qualifications: Bachelors or Masters degree in Electronics, Electrical, or relate engineering disciplines Exposure to scripting languages (Python, Perl, etc.) for automation Contact HR Nikita Chaudhary 8879637539 nikita.chaudhary@enlink.com

Qualifications and Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification. Proficiency in Verilog, System Verilog . Familiarity with industry-standard EDA tools for simulation and debug. Deep experience with UVM-based test benches. Experience with modern programming languages like Python . Knowledge of Arm AMBA protocols such as AXI, APB, and AHB. Understanding of Arm CHI protocol is a plus. Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs. Experience with formal verification techniques, emulation platforms is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills.

Design and development of Chassis Structures such as frame rails, cross members, multi-function brackets, installation of driveline components on Chassis. Delivers value through creation of design concepts by balancing of cross functional needs, collaborating with suppliers to co-develop product solutions. Work closely with colleagues in different Volvo Group global sites, cross functional teams to develop the system and its parts. Development of vehicles structures based on BEV / ICE / alternate energy propulsion systems. Carryout vehicle packaging, durability verification and physical validation needs. Come up with optimized design solutions while working with FE simulation analysts. Work closely with project managers and cross functional teams to anticipate process steps and propose mitigation plans for identified risks. Engineering documentation of drawings, technical requirement, functional specification and managing change. Education, Skills and Experience: BE/ME - Mechanical/Automobile Engineering equivalent with 3 to 6 years of relevant work experience. Hands-on work experience in truck chassis aggregates / equipment installation. Strong in structural design, being analytical and problem-solving ability. Knowledge of design verification and validation is required. Good knowledge of application of GD&T. Extensive hands-on experience in Creo and PDM software, exposure to vehicle packaging is required. Additional requirements: Good networking and interpersonal skills with good verbal and written English communication. Process oriented way of working and a team player mindset are success factors in this role. Be able to recognize the value and importance of providing solutions with the right quality level and on time.

Transport is at the core of modern society. Imagine using your expertise to shape sustainable transport and infrastructure solutions for the future? If you seek to make a difference on a global scale, working with next-gen technologies and the sharpest collaborative teams, then we could be a perfect match. We value your data privacy and therefore do not accept applications via mail. Who we are and what we believe in We are committed to shaping the future landscape of efficient, safe, and sustainable transport solutions. Fulfilling our mission creates countless career opportunities for talents across the group s leading brands and entities. Applying to this job offers you the opportunity to join Volvo Group . Every day, you will be working with some of the sharpest and most creative brains in our field to be able to leave our society in better shape for the next generation. We are passionate about what we do, and we thrive on teamwork. We are almost 100,000 people united around the world by a culture of care, inclusiveness, and empowerment. Group Trucks Technology are seeking talents to help design sustainable transportation solutions for the future. As part of our team, you ll help us by engineering exciting next-gen technologies and contribute to projects that determine new, sustainable solutions. Bring your love of developing systems, working collaboratively, and your advanced skills to a place where you can make an impact. Join our design shift that leaves society in good shape for the next generation. Key Responsibilities: Design and development of Chassis Structures such as frame rails, cross members, multi-function brackets, installation of driveline components on Chassis. Delivers value through creation of design concepts by balancing of cross functional needs, collaborating with suppliers to co-develop product solutions. Work closely with colleagues in different Volvo Group global sites, cross functional teams to develop the system and its parts. Development of vehicles structures based on BEV / ICE / alternate energy propulsion systems. Carryout vehicle packaging, durability verification and physical validation needs. Come up with optimized design solutions while working with FE simulation analysts. Work closely with project managers and cross functional teams to anticipate process steps and propose mitigation plans for identified risks. Engineering documentation of drawings, technical requirement, functional specification and managing change. Education, Skills and Experience: BE/ME - Mechanical/Automobile Engineering equivalent with 3 to 6 years of relevant work experience. Hands-on work experience in truck chassis aggregates / equipment installation. Strong in structural design, being analytical and problem-solving ability. Knowledge of design verification and validation is required. Good knowledge of application of GD&T. Extensive hands-on experience in Creo and PDM software, exposure to vehicle packaging is required. Additional requirements: Good networking and interpersonal skills with good verbal and written English communication. Process oriented way of working and a team player mindset are success factors in this role. Be able to recognize the value and importance of providing solutions with the right quality level and on time.

RTL engineers: (5-15 years of experience) - SoC Design engineer with experience working on SOCs based on ARM Architecture DV engineers : - SOC Verification Experience on ARM Ecosystem - PCIE Experience and also PCIE-VIP usage experience

Design Verification Engineer (5 to 12 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 5 t o 12 Years Openings: 8 Positions Preferred - Immediate to 45 Days (Notice Period) Job Location: ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Notice Period-Prefer less Notice period or serving. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

An RTL Design Verification Engineer role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications. The person: A talented hardware/firmware co-design/verification engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems Debug and solve integration issues with SoC Integration and SoC DV teams Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members Preferred experience: BSc with a minimum of equivalent 5 years relevant experience; or MSc with a minimum of equivalent 3 years; or PhD in a directly related research area and a minimum of 1 year A minimum of equivalent 10 years relevant experience if as advanced level team members Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile) Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets. Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc. Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates Academic credentials: Bachelors Degree or Masters Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Masters Degree preferred

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SENIOR VERIFICATION ENGINEER – SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Mumbai,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. This position is within the process diagnostics and control (PDC) group, which deals with advanced imaging together with cutting edge image processing algorithms and design CAD in order to detect, measure and classify nanometer size defects from semiconductor fabrication process steps. Application engineers are supposed to maximize the performance of our new defect metrology products through a deep and thorough understanding of use-cases in close technical collaboration with leading-edge chip manufacturing customers. Build and maintain strong relationships with customers, including regular communication, feedback and follow-up to ensure customer satisfaction and success. Work closely with internal Product teams including R&D, marketing and internal Account stakeholders to ensure alignment, effective communication and customer engagement. At a higher expertise level, they also contribute to product development roadmap through spec definition and performance validation. They also contribute to SW Application Alpha/Beta phase of qualification in-house and at customer site. Desired qualification Masters / Bachelors degree in Electrical/Electronics Engineering, Mechanical Engineering, Computer Science Engineering or in a related field. 2 to 5 yrs experience in Semiconductor Design, Design Verification, Fabrication or in related field, with focus on technical support, training and/or product development. Sound fundamentals of high-NA DUV imaging/SEM and light-matter/electron-matter interaction Open to on average 50% travel to leading semiconductor chip manufacturing fabs overseas Lab/fab hands-on experience in semiconductor fabrication with layer-wise detailed knowledge of material, process tech and defectivity Detail oriented with strong analytical, problem solving and communication skills Ability to work in a team, and ability to work independently Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 50% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.