Posted:1 week ago| Platform: Foundit logo

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On-site

Job Type

Full Time

Job Description

Key Responsibilities:

test plans for DDR memory interface designs.

Develop UVM/System Verilog-based testbenches

DDR memory interfaces

Collaborate with architecture, RTL, and system teams to understand design intent and corner cases.

Own functional coverage, regression setup, and closure.

Integrate DDR models, controllers, PHYs

Required Skills:

ASIC/IP/SoC verification

SystemVerilog, UVM, and functional coverage methodology

DDR3/DDR4/DDR5/LPDDR protocols

DDR controllers, PHY integration, and JEDEC standards

Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc.

Good scripting skills in Python, Perl, or Shell for automation and regression management.

Excellent debugging and problem-solving skills.

AXI/AHB

Experience working with memory models and timing analysis.

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