630 Cdc Jobs - Page 4

As a Senior Logic Design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performanc...

Project Role :Data Engineer Project Role Description :Design, develop and maintain data solutions for data generation, collection, and processing. Create data pipelines, ensure data quality, and implement ETL (extract, transform and load) processes to migrate and deploy data across systems. Must have skills :Data Engineering, Snowflake Data Warehouse Good to have skills :Machine Learning Minimum 7.5 year(s) of experience is required Educational Qualification :15 years full time education Summary Lead the architecture, strategy, and delivery of enterprise-scale data platforms on Snowflake. Own technical direction for data modeling, ingestion, performance, security, governance, and developer e...

Project Role :Application Support Engineer Project Role Description :Act as software detectives, provide a dynamic service identifying and solving issues within multiple components of critical business systems. Must have skills :Google Cloud Compute Services Good to have skills :AWS Architecture, Microsoft Azure Architecture Minimum 5 year(s) of experience is required Educational Qualification :15 years full time education Summary:As an Application Support Engineer, you will act as software detectives, providing a dynamic service that identifies and resolves issues within various components of critical business systems. Your typical day will involve collaborating with different teams, analyz...

SUMMARY Max CTC : 21,330 Work Timings : US Shift/ Night Shift Contract Duration : 6 months Work location : CDC 5,Shollinganallur Important Pointers Candidate should be flexible to WFO Should be comfortable in International Voice Process. English communication should be excellent. Retention Bonus will be paid as follows 3months 5,000 3+6months -10,000 3+6+6months 10,000 Requirements Any Non Technical Graduates with Good communication skill Eligible. No PG and BE / BTECH Graduate is Eligible Should be able to Speak & Write good English with proper punctuation & grammar. Benefits PF,ESI BOTH WAY CAB(Pickup and drop will be provided) Work From office

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

We are looking for a highly skilled Senior RTL Design Engineer with 8+ years of experience in designing complex digital IPs and SoCs. The ideal candidate should have strong RTL coding, micro-architecture, and synthesis knowledge, with a proven track record of successful tape-outs. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog based on micro-architecture specifications Work on design partitioning, clock domain crossings, and low-power techniques Collaborate with verification, physical design, and DFT teams across the design cycle Perform lint, CDC, and synthesis with timing constraints Optimize design for area, performance, and power Participate in design reviews and documen...

About The Role Project Role : Responsible AI Tech Lead Project Role Description : Ensure the ethical and responsible use of artificial intelligence (AI) technologies. Design and deploy Responsible AI solutions; align AI projects with ethical principles and regulatory requirements. Provide leadership, fosters cross-functional collaboration, and advocates for ethical AI adoption. Must have skills : Microsoft Azure Data Services Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Responsible AI Tech Lead, you will ensure the ethical and responsible use of artificial intelligence technologies. Your typical da...

Role: RTL Lead Experience: 8-12 years Location: HYD & BNG JD: General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required E...

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globa...

As a Principal Data Engineer (Associate Director) at Fidelity, you will be an integral part of the ISS Data Platform Team, responsible for designing, developing, and maintaining scalable data pipelines and architectures to support data ingestion, integration, and analytics. Your key responsibilities will include: - Designing, developing, and maintaining scalable data pipelines and architectures using cloud-based data platform capabilities such as Snowflake and Databricks. - Taking ownership of technical delivery and leading a team of senior and junior developers, providing mentorship and guidance. - Collaborating with enterprise architects, business analysts, and stakeholders to understand d...

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationa...

Role Overview: You will be working as a Data Engineer at VOPAIS in Mumbai, focusing on designing, building, and maintaining scalable data pipelines to ensure data integrity and performance. Your responsibilities will include developing data models, implementing ETL processes, optimizing data infrastructures, and collaborating with cross-functional teams for data-driven decision-making. You will also troubleshoot data-related issues and enhance system efficiency and reliability. Key Responsibilities: - Architect, develop, and optimize real-time and batch data pipelines - Lead integration of Apache Kafka with Databricks, implement Medallion Architecture and CDC workflows - Mentor junior engine...

As part of the DCS group at Microchip Technology, Inc., you will be involved in working on PCIe, CXL based Switches, Re-timers, and flash controllers for data-centers. **Responsibilities:** - Create Micro-Architecture Specification. - Collaborate with team members to design RTL and offer assistance in verification. - Focus on constraint development for CDC, RDC, and synthesis. - Review Test plans provided by the Verification team. - Assist the Emulation and Firmware team during bringup. **Requirements/Qualifications:** - Minimum B.Tech/M.Tech in Electronics or related field. - 10+ years of experience in RTL Design with leadership capabilities. **Key Skills:** - Proficient in VLSI logic desig...

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will play a crucial role in designing cutting-edge solutions that are futuristic and impactful. Your expertise in ASIC RTL Design and proficiency in Verilog/System Verilog will be key assets in this role. You will have the opportunity to work with multiple clock and power domains, integrating and validating various MIPI cores such as CSI/DSI/DPHY/CPHY/other MIPI cores. Your responsibilities will include debug tasks related to CSI/DSI, RTL design and implementation of CSI/DSI controllers, and creating block-level micro-architecture specifications. Key Responsibilities: - Utilize your 10+ years of ASIC RTL Design experience to creat...

Role Overview: You will be joining the Broadcom Central Engineering team as a Multi Skilled RTL, Verification engineer with DFT expertise. In this role, you will work on RTL, Verification, and DFT for Complex Memory, IO subsystems, and Hierarchical Blocks including BIST. This is a great opportunity for individuals who are looking to deepen their expertise in end-to-end Chip development flow with a focus on DFT and Memory BIST, eBIST. Key Responsibilities: - Develop and Verify RTL for Digital subsystems and Memory Subsystems, including BIST. - Perform DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems using Tessent/Embedded MBIST. - Conduct MBIST, ATPG, RSQ Veri...

As a Design Engineer with over 10 years of experience at Qualcomm India Private Limited, your role will involve working on the SoC Interconnect for the next generation System-on-chip (SoC) for various product categories like smartphones, notebooks, smart glasses, and tablets. Your responsibilities will include: - Leading the NoC design as part of the BDC infrastructure (NoC/Interconnect) core team - Specifying, designing, and implementing interconnect and related IPs - Collaborating with SoC team, verification team, physical design team, SoC Floorplan, core teams, and interconnect teams from other sites - Partnering with SoC performance team to meet performance requirements and with silicon ...

As an ASIC/SOC Front End Design Engineer, you will be responsible for setting up ASIC QA flows for RTL design quality checks. Your key responsibilities will include: - Understanding the design intricacies such as top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. - Executing tasks like Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP steps. - Developing clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers. - Identifying and resolving flow errors, design errors, violations, and reviewing reports. - Debugging CDC, RDC issues, and implementing RTL fixes. - Collaborating with the DFX team for DFX c...

As a member of the Cisco SiliconOne team, you will play a crucial role in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by working on complex chips for various aspects of systems and applications. You will have the opportunity to work on Silicon, Hardware, Software, telemetry, security, and more, gaining exposure to all facets of the development process. The team offers a unique blend of a startup culture within the framework of a top-tier networking company. **Key Responsibilities:** - Utilize your ASIC design expertise to contribute to the development cycle from specification to tape-out and lab validation - Demonstrate proficiency in RTL design, including archi...

General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly experienced and motivated professional with a solid background in SoC RTL Design. With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development. You possess a deep understanding of design concept...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on exp...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 12+ years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and ...

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Amazon Web Services (AWS) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure project milestones are met, facilitating discussions to address challenges, and guiding your team through the development process. You ...

7+ years of experience designing and building data pipelines using Apache Spark, Databricks or equivalent bigdata frameworks. Handson expertise with streaming and messaging systems such as Apache Kafka (publish subscribe architecture), Confluent Cloud, RabbitMQ or Azure Event Hub. Experience creating producers, consumers and topics and integrating them into downstream processing. Deep understanding of relational databases and CDC. Proficiency in SQL Server, Oracle or other RDBMSs; experience capturing change events using Debezium or native CDC tools and transforming them for downstream consumption. Proficiency in programming languages such as Python, Scala or Java and solid knowledge of SQL ...

About the Opportunity Job TypeApplication 31 July 2025 TitlePrincipal Data Engineer (Associate Director) DepartmentISS LocationBangalore Reports ToHead of Data Platform - ISS Grade 7 Department Description ISS Data Engineering Chapter is an engineering group comprised of three sub-chapters - Data Engineers, Data Platform and Data Visualisation that supports the ISS Department. Fidelity is embarking on several strategic programmes of work that will create a data platform to support the next evolutionary stage of our Investment Process.These programmes span across asset classes and include Portfolio and Risk Management, Fundamental and Quantitative Research and Trading. Purpose of your role Th...