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4 - 7 years

9 - 12 Lacs

Noida

Hybrid

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Hands-on experience with Oracle & PostgreSQL databases Expertise in Data Analytics, Reporting, & Query Generation Exposure to CDC Streams for Data Replication Strong SQL & DBA skills with CDC knowledge Required Candidate profile Experience: 4-7 years Location: Noida (Hybrid) CTC: Max 12 LPA Notice Period: Max 30 days

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4 - 6 years

7 - 11 Lacs

Hyderabad

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Description: We are seeking a Senior CAD Engineer with specific experience in RTL Synthesis, Timing, and EDA tool environments to contribute. The candidate will be responsible for maintaining and enhancing an established push-button automation flow.

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8 - 10 years

10 - 18 Lacs

Gurgaon

Hybrid

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Experience : 8+ years Location : Gurugram Mode of work: Hybrid Notice Period: Immediate joiners Responsibilities Should have more than 8+ years of extensive experience in Salesforce/nCino Analyse User Stories, understand requirements and raise concern(s) over technical and functional gaps OR unaddressed scenarios (if any) Provide accurate estimates for user stories. Create well-structured technical design for the assigned user story / task by carefully considering the existing implementation and thinking from customers perspective. Develop salesforce platform based good quality, simple, maintainable, highly optimized Perform unit testing of the developed functionality and make sure that it should have negligible functional and technical errors. Develop Test Classes with optimum code coverage as per Salesforce defined best practices Resolve discovered bugs in an efficient manner in first iteration only. Proactively communicate progress and risks to relevant stakeholders Create documentation such as design documents, specifications etc. Help teammates on technical and other aspects, as and when needed. Should be flexible to extend working hours in critical phases. Required Experience 8+ years of total and relevant experience Experience working in an Agile/Scrum development process. Capable of working on multiple fronts Capable of meeting strict timelines Well versed with nCino and Commercial lending domain. Well versed with Lightning Framework, Lightning App Builder. Well versed with Apex Classes, Aura Components, LWC, SOQL, Visualforce and JavaScript Well versed with Salesforce Platform Events, CDC, REST and SOAP based API integrations Well versed with Salesforce Flows, Approval Processes, Process Builder and Workflows Well versed with CI/CD - GitHub Well versed with Salesforce Reports and Dashboards Well versed with Salesforce Data import and export. Working knowledge of JIRA and Confluence Experience developing with VSCode Desired Skills Knowledge of Apex Enterprise Patterns and Apex Design Patterns Working knowledge of Salesforce Digital Experience - Communities / Sites Working knowledge of Lightning Design System Certifications - Salesforce Platform Developer I and II

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7 - 12 years

15 - 25 Lacs

Hyderabad

Hybrid

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Hiring Data_Engineer with Airflow Need 5+ yrs of exp consultants Location: Hyderabad Inida with Hybrid Type: Fulltime Required Skills: Strong Airflow Or Python Skills (for the Platform Uplifting Work) along with Informatica skills. Informatica Power Centre, Power Exchange for CDC. Advanced SQL Skills. We require the candidate to have a minimum of 6 Years of experience in Data Engineer The candidate must have hands-on experience in Airflow for at least 4 years It is not a testing role but a data developer sort of role for platform uplifting Python for data acquisition from different APIs. Unix Shell Scripting.Role & responsibilities

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5 - 10 years

1 - 5 Lacs

Pune

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Qualification - BSC- Nursing, Pbsc Nursing Infection Prevention Policies: Develop, implement and update infection prevention policies and procedures in compliance with relevant guidelines and regulations. Education and Training: Provide education and training to hospital staff, including nurses, physicians and support staff, regarding infection control principles, practices and prevention strategies. Surveillance: Monitor and analyze infection rates within the hospital, conducting surveillance of healthcare-associated infections to identify trends and areas of concern. Isolation Protocols: Establish and enforce isolation protocols for patients with contagious diseases, ensuring proper precautions are taken to prevent the spread of infections. Outbreak Management: Respond to infectious disease outbreaks within the hospital, implementing control measures and coordinating with relevant authorities when necessary. H and Hygiene and Personal Protective Equipment (PPE): Promote proper h and hygiene and the correct use of PPE among hospital staff to reduce the risk of transmission. Cleaning and Disinfection: Ensure that environmental cleaning and disinfection practices meet high standards of cleanliness and hygiene. Device-Associated Infections: Monitor and prevent device-associated infections, such as those related to catheters or ventilators, by implementing best practices. Antibiotic Stewardship: Participate in antibiotic stewardship programs to promote responsible antibiotic use and reduce the development of antibiotic-resistant infections. Data Collection and Reporting: Collect and report infection data to relevant agencies and organizations, maintaining accurate records of infection prevention activities. Compliance and Auditing: Conduct regular audits and assessments to ensure compliance with infection control protocols and recommend improvements when necessary. Quality Improvement: Participate in quality improvement activities to enhance infection control processes and patient safety. Required Skill Sets: 1. Knowledge of infection control principles and guidelines, including those from the CDC and WHO. 2. Strong analytical and problem-solving skills. 3. Excellent communication and teaching skills.

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8 - 13 years

19 - 34 Lacs

Bengaluru

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• 8+ years of strong experience in RTL design • Expertise in RTL coding of complex designs with multiple clock domains • Familiar with UPF and power domain crossing • Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP • Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI • Experience in Spyglass Lint/CDC checks and waiver creation • Experience in formal verification with Cadence LEC • Expertise in Perl/TCL/Python language • Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. • Team player, self-motivated, should be able to work with minimal supervision. Interested share resume or references to Shubhanshi@incise.in

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5 - 7 years

9 - 13 Lacs

Bengaluru

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Job Title: Consultant - Data Analyst Job Description: We are seeking a highly skilled and motivated Consultant - Data Analyst to join our dynamic team. In this role, you will be responsible for analyzing complex data sets, providing actionable insights, and supporting decision-making processes across various projects. Key Responsibilities: - Collaborate with clients to understand their data needs and business objectives. - Collect, clean, and analyze large data sets to identify trends, patterns, and anomalies. - Develop and maintain dashboards and reports to present findings in a clear and effective manner. - Utilize statistical analysis techniques to evaluate data and support business strategies. - Provide recommendations based on data analysis to enhance operational efficiency and drive business growth. - Work closely with cross-functional teams to implement data-driven solutions. - Stay up to date with industry trends and emerging technologies in data analysis. Qualifications: - Bachelor’s degree in Engineering, Master’s degree preferred. - Proven experience as a data analyst or in a similar consulting role. - Proficiency in data analysis tools such as SQL, Excel, R, or Python. - Strong understanding of data visualization tools such as Tableau, Power BI, or similar. - Excellent analytical and problem-solving skills with a keen attention to detail. - Strong communication skills, both written and verbal, with the ability to present complex information clearly. - Ability to work independently and collaboratively in a team environment. Join us and contribute to impactful projects that leverage data to drive success and innovation for our clients. We look forward to your application.

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8 - 13 years

25 - 30 Lacs

Gurgaon

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Position: Data & Information Architecture Lead Department: Digital Technology, Enterprise Architecture, Data & Integration Reporting to: Enterprise Architect Location: Gurgaon Job summary: As a Data and Information Architect, you are part of Enterprise Architecture team focusing on driving innovation, improving delivery effectiveness and enhancing the overall availability and accessibility of data and information to business. You will be responsible for building hybrid solutions on-prem and cloud datalake with seamless integrations across multiple customers facing digital assets, back-end systems and external sources. You bring deep technical expertise in designing and delivering end to end high performance, scalable, secure & flexible data platforms, ETL, MDM, Data Quality, micro services, data Integration solutions using cutting edge/emerging technologies including cloud native and agnostic platforms. You work with the direction from Data Engineering / BI Lead and Enterprise Architect to co-create solutions with the rest of the digital technology, MIS and AI/ML delivery teams . Key responsibilities: Design and optimize architecture of Max Lifes end-to-end data fabric inclusive of data lake, data stores and EDW in alignment with EA guidelines and standards for cataloging and maintaining data repositories Undertake detailed analysis of the information management requirements across all systems, platforms & applications to guide the development of info. management standards Lead the design of the information architecture, across multiple data types working closely with various business partners/consumers, MIS team, AI/ML team and other departments to design, deliver and govern future proof data assets and solutions Define, develop and communicate information management standards relating to the location, media type and security requirements to facilitate efficient and secure management of all data elements Design and ensure delivery excellence for a) large & complex data transformation programs, b) small and nimble data initiatives to realize quick gains, c) work with OEMs and Partners to bring the best tools and delivery methods. Define, design, develop and maintain organization data models that meet immediate and future needs Drive data domain modeling, data engineering and data resiliency design standards across the micro services and analytics application fabric for autonomy, agility and scale Ensure data is treated as an asset across the MLI ecosystem through establishing right governance & curation, data quality and master data management processes and tooling Ensure regulatory issues are considered surrounding information assets (such as consumer privacy laws, data retention policies, outsourced data and specific industry guidelines are adhered to) Coordinate new development activities and ensure they are consistent and well integrated with the established MLI information architecture delivering desired business outcomes Other responsibilities: Provide technical expertise in solving/troubleshooting performance & other non-functional requirements Provide ongoing guidance to project teams on impacted information flows & ensure alignment to overall information architecture Collaborate with ecosystem partners to identify synergies across information flow & management & information architecture Experiment, explore and demonstrate application of new technologies by means of conducting quick prototypes to solve business problems. Focus on continuous service improvement and thought leadership, drive strategic initiatives to help business and partners to achieve their goals Measures of Success: Alignment of data assets to MLI data strategy and data architecture High agility in provisioning data to consumers enhancing data accessibility and democratization of data across MLI Solution aligned with information/ data management guiding principles/standards and data models with data classification standards Exceptional user(internal/external) experience, automation and operational efficiency by adoption of new cutting edge technology solutions to solve business problems Trusted partnership with other departments of IT and business Key competencies/skills required Deep understanding of the data and information architecture discipline, processes, concepts and best practices Hands on expertise in building and implementing data architecture for large enterprises Proven architecture modelling skills, strong analytics and reporting experience Strong Data Design, management and maintenance experience Strong experience on data modelling tools Extensive experience in areas of cloud native lake technologies e.g. AWS Native Lake Solution Understanding of BFSI domain, Open Architecture and application integration discipline, concepts and best practices Define cost control mechanisms by suggesting architectural changes & optimizing resource utilization Any prior experience on Implementation of AI, Data Analytics will be a plus Desired qualifications and experience: B.E / MCA from a reputed institute 8+ years of experience with the technical analysis, architecting and implementation of data warehousing and data lake solutions on-premisis and on-cloud (preferable AWS Native Lake Platform and services, Glue, EMR, DMS etc.) 5+ years of hands-on experience data engineering & modelling, reporting, analytics platforms Relational Database, NoSQL, Hadoop, SPARK, Informatica, CDC, SAS, Visualization and Dashboarding tools/libraries, BODS, Apache NiFi, EMR, Erwin and/or Rational Rose, real-time data streaming tools (kafka, kinesis) etc. Should have architected and delivered at least 3+ EDW, Data Lake projects 4+ experience of designing and modernizing existing data stores/EDW on cloud platform Experience in Insurance and BFSI domain is a plus Experience in presenting data architecture for specific business needs to peers and senior management Should be working or should have worked with reputed organizations or startups

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5 - 10 years

20 - 35 Lacs

Pune, Bengaluru, Hyderabad

Hybrid

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Greeting form Globex Digital..! Please find the job description for _RTL Engineer _MNC Client JD: Sr RTL Engineer Experience: 5-15 Years Mode: Full Time Location: Bangalore,Hyderabad, Pune. NP: Immediate-90days Senior ASIC/SoC RTL Engineer/Lead 5-15yrs 1) Expertise in SoC/IP design 2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog 3) In depth knowledge on RTL quality checks (Lint, CDC) 4) Knowledge of synthesis and low power is a plus 5) Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) 6) Good understanding of timing concepts 7) Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPI 8) Expertise in setting up and using tools like a. Spyglass Lint/CDC b. Synopsys DC c. Verdi/Xcellium 9) Understanding of scripting languages like Make flow, Perl ,shell, python etc 10) Understanding of processor architecture and/or ARM debug architecture is a plus 11) Able to help and debug issues for multiple subsystems 12) Able to create/review design documents for multiple subsystems 13) Able to support physical design, verification, DFT and SW teams on design queries and reviews. interested Candidate Can forward their Profile rahul@globexdigitalcorp.com with following details Please fill the Details below: Full Name Contact Number Alternate Number Email ID Total Experience Relevant Experience Current CTC Expected CTC Offers Notice Period/LWD Reason for Change Current Company Pay Roll Company LinkedIn Current Location Preferred Location

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7 - 11 years

20 - 25 Lacs

Bengaluru

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About The Role About The Role As a SoC Micro-Architect, you will be responsible to work on feasibility of feature requests, partitioning them effectively and proposing an effective implementation which meets the desired Power, Performance and Area targets. You will need to work with cross functional teams and will be responsible for defining Micro-architecture specifications. Work with SoC Architecture, Platform, Firmware, Logic, Validation, Physical and DFT teams in defining and guiding SoC design implementationResponsibilities and duties:* Work with SoC Architecture to interpret high level architecture specs* Drive feature analysis and scoping* Define micro-architecture specifications.* Perform feasibility study on different third-party IP and drive integration* Drive RTL Implementation team, work closely with Backend team on floorplan, Constraints definition and timing analysis.* Closely work with Verification team and help define test plan and debug design.* Participate in design reviews.* Participate and drive timing convergence for high-speed designs including micro- architecture optimizations* Collaborate with internal and external team members on architectural decisions, development flows and methodologies* Lead end to end feature implementation and enablement.* Responsible for meeting SoC design quality, performance and power goals Qualifications Required qualifications:Educational requirements for this position are a BSEE/CE minimum, MS preferred.Also required 18 plus years' experience in IC/SoC Design and Micro Architecture* Experience in all phases of logic development lifecycle from high-level specification to tape-out and production* Expertise in one or more of the following domains* AI server Micro Architecture* Power Management* Cache Management* Inter die IOs Micro Architecture* HBM IOs Micro ArchitectureBehavioral Traits* Excellent communication and documentation skill.* Must be skilled to influence in heavily matrixed environment.* Capable to operate in ambiguity where roles may not be clearly defined or teams across multiple/functions and IP/SOC must be pulled together.In this role you will be part for the Data center group (XEG - India) design team, working on next-generation Server and AI products. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

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3 - 6 years

12 - 16 Lacs

Bengaluru

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About The Role Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Hands on experience in IP RTL, Microarchitecture, TFM, synthesis, cdc, lint, spyglass, rdc. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc) Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 8-14 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited toSystem Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools and flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

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3 - 6 years

12 - 16 Lacs

Bengaluru

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About The Role Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited toSystem Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

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5 - 8 years

12 - 20 Lacs

Bengaluru

Hybrid

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Job Title: IICS Admin Location: Bangalore , India Job Description: We are seeking a Informatica Admin skilled in IICS and Mass Data ingestion, replication & automation. To join our team, an ideal candidate will have extensive experience in mass data ingestion, IICS, data cataloging, data governance, and data replication. This role is critical for ensuring the seamless integration and management of our data systems. Apply Here: https://app.fabrichq.ai/jobs/4eba93b1-fd39-4e07-839f-c9660ce4a3b6 About the company Fabric is an AI-powered technical screening platform that helps developers connect with their next opportunity. When you apply through Fabric, you'll participate in a thorough technical interview with our AI system, which you can complete at any time that works for you. The interview focuses on understanding your actual technical experience and problem-solving abilities, not just keywords on your resume. If you pass the technical assessment, your profile can receive up to 15 interview invites from different companies. We work with some of India's leading tech companies, which means your single interview with Fabric could open doors to multiple promising opportunities. Fabric streamlines the early stages of the hiring process so you can spend less time in preliminary screenings and more time having meaningful conversations with potential employers. Key Responsibilities: Data Ingestion : Design and implement data ingestion processes to ensure efficient and accurate data flow from various sources. SQL & MSSQL Database Management: Develop and maintain SQL queries, stored procedures, and manage MSSQL databases to support data operations. Data Cataloging: Create and maintain a comprehensive data catalog to ensure data is easily discoverable and accessible. Data Governance : Implement and enforce data governance policies to ensure data quality, security, and compliance. Data Replication: Set up and manage data replication processes to ensure data consistency and availability across systems. Utilizing IICS for tasks/job automation. Understanding Change Data Capture (CDC). Creating and implementing ETL pipelines with standard industry tools. Collaboration: Work closely with data engineers, analysts, and other stakeholders to understand data requirements and deliver solutions. Qualifications: Proven experience with Informatica tools and technologies. Strong proficiency in SQL and MSSQL databases. Experience with data cataloging and data governance practices. Knowledge of data replication techniques and tools. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. Proficiency in Informatica IICS Administration and SQL Preferred Qualifications: Experience in a similar role within a fast-paced environment. Certification in Informatica or related technologies. Knowledgeable about IBM I DB2 Database, Oracle, and SQL servers

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10 - 12 years

12 - 14 Lacs

Bengaluru

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Being part of DCS group, candidate will be working on PCIe, CXL based Switches, Re-timers and flash controllers for data-centers. Responsibilites: Create Micro-Architecture Specification. Work with team members to design RTL and provide support to verification. Work on constraint development for CDC, RDC and synthesis. Review Test plans from Verification team. Support Emulation and Firmware team in bringup. Qualifications/Requirements Qualifications/Requirements Minimum B.Tech/M.Tech in Electronics or related field. 10+ years of experience in RTL Design and timing aspects of IC design, with leadership capability. Key Skills: Expertise in VLSI logic design, understanding architecture and design planning. Expertise in synthesis/debugging, and timing closure. Knowledge of protocols like PCIe, CXL, AXI, AHB, I3C etc. Proficiency in Tcl and Perl scripting. Power planning and implementation techniques. Proficiency in CDC, RDC and constraint development. Excellent debugging, analytical, and leadership skills. Strong communication skills and interpersonal abilities.

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2 - 7 years

4 - 9 Lacs

Ludhiana, Mysore, Mohali

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You will work with our customers in developing and modernizing applications that can fully leverage the advanced and new capabilities the IBM zOS Mainframes, interoperate with and extend to the IBM Redhat OCP and other cloud ecosystem. You will work on challenging and interesting initiatives, at the forefront of Mainframe Application Development and Cloud Adoption. Identify, evaluate, recommend and work with IBM Partner Ecosystem for niche Language and Data Migration Implement DevOps practices such as infrastructure as code, continuous integration and automated testing Excellent communication skills with ability to simplify complex problems for a variety of stake holders including Client Architects and CXOs Experienced in Estimation process and practices Domain exposure to Financial Service, Retail, Healthcare Ability to lead technical delivery teams and influence client executives Required education Non-Degree Program Preferred education Bachelor's Degree Required technical and professional expertise 12+ years of hands-on experience in designing, developing and maintaining large scale mainframe applications Expert in core mainframe technologieszOS, Cobol, CICS, DB2, JCL and VSAM Good understanding of NextGen Mainframe Application Development and Testing Tools like IDz, ADFz, DBB, Git, Jenkins and UCDz Good understanding of SCM and Schedulers on mainframe Experience in Mainframe Application and Data Integration solutions like MQ, CTG, CICS Web Services, zOSConnect, ETL and CDC Preferred technical and professional experience Exposure / ability to quickly pick up additional technologies where neededIMS DB/DC, Assembler, PL/1 etc Experience in using Source Code analysis tools like ADDI, CAST AIP, Microfocus EA Location - Ludhiana,Mohali,Mysuru,Ahmedabad,Chandigarh,Coimbatore,Dehradun,Thiruvananthapuram,Indore,Lucknow,Mangaluru,Hyderabad,Kolkata,Mumbai,Raipura,Pune,Gurugram,Surat,Chennai,Noida,Visakhapatnam,Navi Mumbai,Bengaluru,Kochi,Jaipur,Bhubaneswar,New Delhi

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7 - 12 years

9 - 14 Lacs

Bengaluru

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Project Role : Business Analyst Project Role Description : Analyze an organization and design its processes and systems, assessing the business model and its integration with technology. Assess current state, identify customer requirements, and define the future state and/or business solution. Research, gather and synthesize information. Must have skills : EPIC Systems Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : A 15 years full time education is required. Summary :As a Business Analyst with expertise in EPIC Systems, you will be responsible for analyzing an organization and designing its processes and systems, assessing the business model and its integration with technology. Your typical day will involve researching, gathering, and synthesizing information to assess the current state, identify customer requirements, and define the future state and/or business solution. Roles & Responsibilities:- Lead the analysis of an organization's processes and systems, assessing the business model and its integration with technology.- Assess the current state, identify customer requirements, and define the future state and/or business solution.- Research, gather, and synthesize information to support the analysis and design of processes and systems.- Collaborate with cross-functional teams to ensure alignment and integration of business processes and systems.- Communicate technical findings effectively to stakeholders, utilizing data visualization tools for clarity. Professional & Technical Skills:- Must To Have Skills:Expertise in EPIC Systems.- Good To Have Skills:No Technology Specialization.- Strong understanding of business processes and systems.- Experience in analyzing and designing business processes and systems.- Experience in collaborating with cross-functional teams.- Solid grasp of data visualization tools. Additional Information:- The candidate should have a minimum of 7.5 years of experience in EPIC Systems.- The ideal candidate will possess a strong educational background in business, technology, or a related field, along with a proven track record of delivering impactful business-driven solutions.- This position is based at our Bengaluru office. Qualifications A 15 years full time education is required.

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3 - 5 years

5 - 9 Lacs

Jaipur

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Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP BusinessObjects Data Services Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Project Role :Application Developer Project Role Description :Design, build and configure applications to meet business process and application requirements. Key Responsibilities:1)Work with functional SMEs to review requirements, field mapping documents from source to target2)Create ETL jobs from scratch and implement simple to complex logic as per mapping document3)Perform Extraction, transformation / source to target mapping and load into Files, Database.4)Performance analysis of existing jobs, and work on enhancements based on new requirements.5)Prepare FD, TD, UT, Cutover documentation Technical Experience:1)Greater than 4 years of ETL Development experience 2)Should have worked independently on ETL Development project at least 1 end to end development project.3)Should understand the basic ETL design concepts like CDC, SCD, Transpose, Updates, Validation4)Having worked with files delimited, fixed width etc will be an added advantage. Professional Attributes :1)Good communication skills2)Should be hands on Collaborative and professional attitude 3)Ability to learn new tools & technologies Educational Qualification :15 years of fulltime education with BE/B Tech or equivalent Qualifications 15 years full time education

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4 - 9 years

20 - 30 Lacs

Bengaluru, Hyderabad

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Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/System Verilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related fields. 4-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment. Preferred Skills : Experience with complex subsystems such as memory controllers, interconnects, or high-speed I/O. Prior experience working with large, cross-functional teams and managing design schedules. Experience with software tools for RTL analysis and optimization. Hands-on experience in leading ASIC projects from specification to production. Perks and benefits According to company norms

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5 - 10 years

7 - 12 Lacs

Bengaluru

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Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function :Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leadsDeveloping the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoCDesign and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.Analyze reports/waivers or run various tools :Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

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3 - 8 years

5 - 10 Lacs

Chennai

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Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 6-9 years of experience in SoC design Educational Requirements:6+ years of experience with a Bachelor"™s/ Master"™s degree in Electrical engineering

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2 - 7 years

4 - 9 Lacs

Hyderabad

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Job Area: Information Technology Group, Information Technology Group > Cyber Security Engineering General Summary: Job Overview This role will be responsible for supporting 24x7 operations thus requires working night / weekend shifts on a rotational basis to support the business requirements of the organization Primary responsibilities include monitoring and triaging all security events coming into SOC / CDC from multiple sources. Security events include but not limited to; social engineering attacks, malware, DDoS, data exfiltration, ransomware etc.Triage for first 20 minutes as per standard operating procedure, and post which engage Tier2 for further assistanceIdentifying and Analyzing of security event and incident data by leveraging Orchestration tool workflows and knowledge baseUpdating the Ticketing system thoroughly and timelyCommunicating with stake holders for making sound recommendations on mitigation and or prevention techniquesFollow up and resolution of issues/tickets timely per SLA"™sFollow-up on pending tickets and issues ensuring SLA"™sWorking closely with Tier3 teamsEscalating security events in a timely mannerStaying current with new Use Cases and process changesActively participate in brown bag sessions Min. Qualifications The individual must also have a good awareness of current and developing security threats and technologiesStrong proficiency in security event investigations, also in written and spoken EnglishStrong interpersonal skills and a good team playerPrior professional services experience in 24x7 SOC or CDC operations is desiredBachelor"™s degree or Master"™s Degree in Computer Sciences or in Cyber Security Preferred Qualifications 3 - 5 years of experience working in a SIEM tool with strong background in security incident response and system operationsCEH, Security+, OSCP or other industry-relevant cyber-security certifications and ITIL V3.0 knowledge is a plus Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of cybersecurity-relevant work experience. OR High school diploma or equivalent and 4+ years of cybersecurity-relevant work experience. Physical Requirements: Frequently transports and installs equipment up to 40 lbs.

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3 - 6 years

5 - 8 Lacs

Chennai

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Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience

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5 - 10 years

7 - 12 Lacs

Bengaluru

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Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

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5 - 10 years

19 - 34 Lacs

Bengaluru

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• 5 to 10 years of strong experience in RTL design • Expertise in RTL coding of complex designs with multiple clock domains • Familiar with UPF and power domain crossing • Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP • Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI • Experience in Spyglass Lint/CDC checks and waiver creation • Experience in formal verification with Cadence LEC • Expertise in Perl/TCL/Python language • Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. • Team player, self-motivated, should be able to work with minimal supervision. Interested share resume or references to Shubhanshi@incise.in

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2 - 6 years

2 - 4 Lacs

Bengaluru

Remote

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Hello, We have an great opportunity for the role of Informatica Administrator. - Mandatory Skills : Informatica Administration ( Power exchange/Power center / Cdc publisher) -Relevant Exp : 2+ Yrs -Immediate Joiners to 15 days Preferred -Job location- 100% Remote Ask me about awesome referral award of INR 50000 Check global opportunity at iitjobs.com

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