190 Cdc Jobs - Page 5

Responsibilities Build microarchitectures for various digital designs and components. Implement IP in RTL using industry-standard methodologies and tools. Perform CDC (Clock Domain Crossing) and Lint analysis to ensure design reliability and correctness. Utilize scripting languages such as TCL, Perl, and Python for automation and tool integration. Generate synthesis constraints to facilitate the synthesis process and ensure optimal performance. Collaborate with cross-functional teams to validate design and address any issues that arise during implementation. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 4 to 8 years of experience in RTL design and verification. Strong knowledge of microarchitecture principles and RTL coding practices. Hands-on experience in UPF (Unified Power Format) for low power design. Proficiency in CDC and Lint analysis tools. Familiarity with scripting languages: TCL, Perl, and Python. Experience in generating synthesis constraints for various RTL designs.

Genpact (NYSE: G) is a global professional services and solutions firm delivering outcomes that shape the future. Our 125,000+ people across 30+ countries are driven by our innate curiosity, entrepreneurial agility, and desire to create lasting value for clients. Powered by our purpose - the relentless pursuit of a world that works better for people - we serve and transform leading enterprises, including the Fortune Global 500, with our deep business and industry knowledge, digital operations services, and expertise in data, technology, and AI . Inviting applications for the role of Lead Consulta nt- Snowflake Data Engineer ( Python+Cloud ) ! In this role, the Snowflake Data Engineer is responsible for providing technical direction and lead a group of one or more developer to address a goal. Job Description: Experience in IT industry Working experience with building productionized data ingestion and processing data pipelines in Snowflake Strong understanding on Snowflake Architecture Fully well-versed with data warehousing concepts. Expertise and excellent understanding of Snowflake features and integration of Snowflake with other data processing. Able to create the data pipeline for ETL/ELT Excellent presentation and communication skills, both written and verbal Ability to problem solve and architect in an environment with unclear requirements. Able to create the high level and low-level design document based on requirement. Hands on experience in configuration, troubleshooting, testing and managing data platforms, on premises or in the cloud. Awareness on data visualisation tools and methodologies Work independently on business problems and generate meaningful insights Good to have some experience/knowledge on Snowpark or Streamlit or GenAI but not mandatory. Should have experience on implementing Snowflake Best Practices Snowflake SnowPro Core Certification is must. Roles and Responsibilities: Requirement gathering, creating design document, providing solutions to customer, work with offshore team etc. Writing SQL queries against Snowflake, developing scripts to do Extract, Load, and Transform data. Hands-on experience with Snowflake utilities such as SnowSQL , Bulk copy, Snowpipe , Tasks, Streams, Time travel, Cloning, Optimizer, Metadata Manager, data sharing, stored procedures and UDFs, Snowsight . Have experience with Snowflake cloud data warehouse and AWS S3 bucket or Azure blob storage container for integrating data from multiple source system. Should have have some exp on AWS services (S3, Glue, Lambda) or Azure services ( Blob Storage, ADLS gen2, ADF) Should have good experience in Python/ Pyspark.integration with Snowflake and cloud (AWS/Azure) with ability to leverage cloud services for data processing and storage. Proficiency in Python programming language, including knowledge of data types, variables, functions, loops, conditionals, and other Python-specific concepts. Knowledge of ETL (Extract, Transform, Load) processes and tools, and ability to design and develop efficient ETL jobs using Python and Pyspark . Should have some experience on Snowflake RBAC and data security. Should have good experience in implementing CDC or SCD type-2 . Should have good experience in implementing Snowflake Best Practices In-depth understanding of Data Warehouse, ETL concepts and Data Modelling Experience in requirement gathering, analysis, designing, development, and deployment. Should Have experience building data ingestion pipeline Optimize and tune data pipelines for performance and scalability Able to communicate with clients and lead team. Proficiency in working with Airflow or other workflow management tools for scheduling and managing ETL jobs. Good to have experience in deployment using CI/CD tools and exp in repositories like Azure repo , Github etc. Qualifications we seek in you! Minimum qualifications B.E./ Masters in Computer Science , Information technology, or Computer engineering or any equivalent degree with good IT experience and relevant as Snowflake Data Engineer. Skill Metrix: Snowflake, Python/ PySpark , AWS/Azure, ETL concepts, & Data Warehousing concepts Genpact is an Equal Opportunity Employer and considers applicants for all positions without regard to race, color , religion or belief, sex, age, national origin, citizenship status, marital status, military/veteran status, genetic information, sexual orientation, gender identity, physical or mental disability or any other characteristic protected by applicable laws. Genpact is committed to creating a dynamic work environment that values respect and integrity, customer focus, and innovation. For more information, visit . Follow us on Twitter, Facebook, LinkedIn, and YouTube. Furthermore, please do note that Genpact does not charge fees to process job applications and applicants are not required to pay to participate in our hiring process in any other way. Examples of such scams include purchasing a %27starter kit,%27 paying to apply, or purchasing equipment or training .

hiring for RTL design Lead, for Hyderabad location , Exp - 8+ yrs RTL Design, SOC integration, CDC / Lint, IP Enhancement. Interested, kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com

Join our team as a Transport Network Engineer, where youll work on building and maintaining large-scale optical transport systems. Youll be involved in network commissioning, troubleshooting, and supporting NPI activities, while contributing to project planning, documentation, and technical coordination across multi-domain environments. You Have: Hands-on experience with DWDM & OTN network deployment, integration, and troubleshooting. Proficiency with optical test tools such as OTDR, Power Meters, CD/PMD Analyzers, and BERT. Deep understanding of transport technologiesGMPLS (L0/L1), ASON, SDH, Ethernet, MPLS-TP. Experience in creating and maintaining engineering documentation and Methods of Procedure (MOPs). Proven ability to lead network commissioning, maintenance, and NPI (New Product Introduction ) activities. Excellent communication skills and ability to collaborate with cross-functional and field teams. It Would Be Nice If You Also Had: Experience with1830 PSS platforms (e.g., PSS-4/16/32, PSS-36/64, PSS-8/16II). Familiarity with Flexgrid, CDC architectures, and Raman amplification, Deploy, configure, and support large-scale optical networks (DWDM & OTN), spanning long-haul, metro, and data center interconnects. Design and maintain Engineering Design Packages for metro, regional, and long-haul optical systems. Perform network turn-up, integration, testing, commissioning, and maintenance activities, ensuring design validation and operational readiness. Troubleshoot and resolve complex network build and operational issues using advanced tools like OTDR, CD/PMD analyzers, and BERT. Lead and execute customer-facing activities such as demos, PoCs, field trials, and New Product Introduction (NPI) validations. Create, review, and approve Methods of Procedures (MOPs) and develop comprehensive system support documentation. Provide technical expertise to field teams and deliver internal training on new technologies and solutions. Contribute to network design and project management for hardware deployments, upgrades, and migrations, ensuring best practices are followed across transport domains.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: ASIC Design. Experience5-8 Years.

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Long Description 4. Analog Circuit Design : Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Experience - 7+ Yrs + Lead/Architect Location - Bangalore 5. DFT - ATPG, MBIST Location - Bangalore, Kochi, Pune, Hyderabad Experience - 7 years + DFT Lead Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains – all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. : Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Database Administrator (DBA) Job Summary We are seeking a senior DBA to join our team. The ideal candidate will have a deep understanding of database architecture, strong knowledge of database management systems, and hands-on experience with AWS RDS, Oracle Cloud Infrastructure (OCI), PostgreSQL, MySQL and Oracle. As a Senior DBA, you will be responsible for managing and optimizing databases across multiple cloud platforms (AWS, OCI), ensuring high performance, security, and reliability. Additionally, you will be supporting for IBM IIDR CDC data mirroring between AS400 and Oracle. Responsibilities: Migrate existing platforms to the current engineered standards in multi-cloud environment. Collaborate with solutions architects and product engineers to enhance database infrastructure. Test backup and recovery scenarios and formulate disaster recovery procedures. Install, maintain, and troubleshoot PostgreSQL, MySQL, Oracle databases in multi cloud environment AWS and OCI Supporting on IBM Infosphere Data Replication, a CDC product on day-to-day data mirroring between AS400 and Oracle database. Manage daily database-related tasks, including documentation, performance monitoring and tuning, backups recovery, patching maintenance, DR, security hardening and incident management. Create, update and maintaining process documentation. Implement and monitor security measures for databases and OCI resources. Mentor fellow DBAs and provide input into architecture and design. Automate database tasks where possible. Manage databases for financial institutions, ensuring compliance and security. Qualifications: Bachelor’s or University Degree in Computer Science, Engineering, or related field. 7 - 9 years of proven work experience as a DBA with at least 3 years of experience working on OCI ExaCS/ExaCC and AWS RDS. Strong knowledge of PostgreSQL, MySQL, Oracle and other relevant technologies. Proficiency in writing complex SQL queries and optimizing database performance. PostgreSQL and MySQL certification Oracle certification AWS Certification OCI certification IBM Infosphere Data Replication certification / experience Deep understanding of database architecture – PostgreSQL, MySQL, Oracle Experience with database performance tuning and optimization. Familiarity with various database tools and automation. Positive attitude and willingness to take initiative

Job Title: Data Engineer II (Python, SQL) Experience: 3 to 6 years Location: Bangalore, Karnataka (Work from office, 5 days a week) Role: Data Engineer II (Python, SQL) As a Data Engineer II, you will work on designing, building, and maintaining scalable data pipelines. Youll collaborate across data analytics, marketing, data science, and product teams to drive insights and AI/ML integration using robust and efficient data infrastructure. Key Responsibilities: Design, develop and maintain end-to-end data pipelines (ETL/ELT). Ingest, clean, transform, and curate data for analytics and ML usage. Work with orchestration tools like Airflow to schedule and manage workflows. Implement data extraction using batch, CDC, and real-time tools (e.g., Debezium, Kafka Connect). Build data models and enable real-time and batch processing using Spark and AWS services. Collaborate with DevOps and architects for system scalability and performance. Optimize Redshift-based data solutions for performance and reliability. Must-Have Skills & Experience: 3+ years in Data Engineering or Data Science with strong ETL and pipeline experience. Expertise in Python and SQL . Strong experience in Data Warehousing , Data Lakes , Data Modeling , and Ingestion . Working knowledge of Airflow or similar orchestration tools. Hands-on with data extraction techniques like CDC , batch-based, using Debezium, Kafka Connect, AWS DMS . Experience with AWS Services : Glue, Redshift, Lambda, EMR, Athena, MWAA, SQS, etc. Knowledge of Spark or similar distributed systems. Experience with queuing/messaging systems like SQS , Kinesis , RabbitMQ .

How to Apply: Application Mode: Applications for this position will be accepted ONLY ONLINE through: BHEL Recruitment Website BHEL Careers Page No other mode of application will be entertained. Job description RECRUITMENT OF EXPERIENCED ENGINEERING PROFESSIONALS ON LATERAL BASIS FOR ELECTRONICS DIVISION (EDN), BANGALORE Senior Engineer - Embedded FPGA Design (LE05) The prospective candidate should have at least 5 years of post-qualification experience for applying to Senior Engineer (E2) position and exposure in handling the following areas in relevant industry shall be given preference: Role & responsibilities Experience for Senior Engineer :- Working experience in: Thorough experience of using Intel/ Altera development tool chains Experience in RTL design using VHDL/verilog - design complexity 16K Understand CDC, STA and other timing considerations in the context of FPGA. Advanced knowledge of clocking, memory and other FPGA needs. Knowledge of Designing of control cards using Intel FPGA devices Understanding Latest Standard Communication Protocols ( CAN,TCP_IP, and or MVB/TRDP ) Experience of functional testing and test tools Interfacing with the Hardware, software, PCB design and System Design Team Desirable Skills: Candidate should possess inspiring leadership qualities and in-depth of knowledge about the execution and delivery of electronic modules/ sub-assemblies/systems for control & instrumentation or Propulsion equipment of Rail Transportation applications or other relevant applications with insatiable quest for excellence and passion for continuous professional growth Design of IP cores/protocols: Ethernet redundancy /HDLC, SPI etc., Design based on System On Chip(SOC) Experience of best practices in software development processes Experience of continuous integration, automated test tools and frameworks. Exposure of coding standards for defence techniques and standards such as MISRA Should have experience in managing conflicting priorities and cross functional teams to successfully implement complex projects. Grade & Pay Scale Senior Engineer: E2 - Rs 70000 - 200000

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

Inviting applications for the role of Lead Consultant -Data Engineer! . Design, document & implement the data pipelines to feed data models for subsequent consumption in Snowflake using dbt, and airflow. . Ensure correctness and completeness of the data being transformed via engineering pipelines for end consumption in Analytical Dashboards. . Actively monitor and triage technical challenges in critical situations that require immediate resolution. . Evaluate viable technical solutions and share MVPs or PoCs in support of the research . Develop relationships with external stakeholders to maintain awareness of data and security issues and trends . Review work from other tech team members and provide feedback for growth . Implement Data Performance and data security policies that align with governance objectives and regulatory requirements . Effectively mentor and develop your team members . You have experience in data warehousing, data modeling, and the building of data engineering pipelines. . You are well versed in data engineering methods, such as ETL and ELT techniques through scripting and/or tooling. . You are good at analyzing performance bottlenecks and providing enhancement recommendations you have a passion for customer service and a desire to learn and grow as a professional and a technologist. . Strong analytical skills related to working with structured, semi-structured, and unstructured datasets. . Collaborating with product owners to identify requirements, define desired and deliver trusted results. . Building processes supporting data transformation, data structures, metadata, dependency, and workload management. . In this role, SQL is heavily focused. An ideal candidate must have hands-on experience with SQL database design. Plus, Python. . Demonstrably deep understanding of SQL (level: advanced) and analytical data warehouses (Snowflake preferred). . Demonstrated ability to write new code i.e., well-documented and stored in a version control system (we use GitHub & Bitbucket) . Extremely talented in applying SCD, CDC, and DQ/DV framework. . Familiar with JIRA & Confluence. . Must have exposure to technologies such as dbt, Apache airflow, and Snowflake. . Desire to continually keep up with advancements in data engineering practices. Qualifications we seek in you! Minimum qualifications: Essential Education Bachelor%27s degree or equivalent combination of education and experience. Bachelor%27s degree in information science, data management, computer science or related field preferred. Essential Experience & Job Requirements . IT experience with a major focus on data warehouse/database-related projects . Must have exposure to technologies such as dbt, Apache Airflow, and Snowflake. . Experience in other data platforms: Oracle, SQL Server, MDM, etc . Expertise in writing SQL and database objects - Stored procedures, functions, and views. Hands-on experience in ETL/ELT and data security, SQL performance optimization and job orchestration tools and technologies e.g., dbt, APIs, Apache Airflow, etc. . Experience in data modeling and relational database design . Well-versed in applying SCD, CDC, and DQ/DV framework. . Demonstrate ability to write new code i.e., well-documented and stored in a version control system (we use GitHub & Bitbucket) . Good to have experience with Cloud Platforms such as AWS, Azure, GCP and Snowflake . Good to have strong programming/ scripting skills (Python, PowerShell, etc.) . Experience working with agile methodologies (Scrum, Kanban) and Meta Scrum with cross-functional teams (Product Owners, Scrum Master, Architects, and data SMEs) o Excellent written, and oral communication and presentation skills to present architecture, features, and solution recommendations Global functional product portfolio technical leaders (Finance, HR, Marketing, Legal, Risk, IT), product owners, functional area teams across levels o Global Data Product Portfolio Management & teams (Enterprise Data Model, Data Catalog, Master Data Management) Preferred Qualifications Knowledge of AWS cloud, and Python is a plus. . . . . . .

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

What you will do In this vital role, you will be responsible for the end-to-end development of an enterprise analytics and data mastering solution using Databricks and Power BI. This role requires expertise in both data architecture and analytics, with the ability to create scalable, reliable, and impactful enterprise solutions that research cohort-building and advanced research pipeline. The ideal candidate will have experience creating and surfacing large unified repositories of human data, based on integrations from multiple repositories and solutions, and be extraordinarily skilled with data analysis and profiling. You will collaborate closely with key customers, product team members, and related IT teams, to design and implement data models, integrate data from various sources, and ensure best practices for data governance and security. The ideal candidate will have a good background in data warehousing, ETL, Databricks, Power BI, and enterprise data mastering. Design and build scalable enterprise analytics solutions using Databricks, Power BI, and other modern data tools. Leverage data virtualization, ETL, and semantic layers to balance need for unification, performance, and data transformation with goal to reduce data proliferation Break down features into work that aligns with the architectural direction runway Participate hands-on in pilots and proofs-of-concept for new patterns Create robust documentation from data analysis and profiling, and proposed designs and data logic Develop advanced sql queries to profile, and unify data Develop data processing code in sql, along with semantic views to prepare data for reporting Develop PowerBI Models and reporting packages Design robust data models, and processing layers, that support both analytical processing and operational reporting needs. Design and develop solutions based on best practices for data governance, security, and compliance within Databricks and Power BI environments. Ensure the integration of data systems with other enterprise applications, creating seamless data flows across platforms. Develop and maintain Power BI solutions, ensuring data models and reports are optimized for performance and scalability. Collaborate with key customers to define data requirements, functional specifications, and project goals. Continuously evaluate and adopt new technologies and methodologies to enhance the architecture and performance of data solutions. What we expect of you We are all different, yet we all use our unique contributions to serve patients. The R&D Data Catalyst Team is responsible for building Data Searching, Cohort Building, and Knowledge Management tools that provide the Amgen scientific community with visibility to Amgens wealth of human datasets, projects and study histories, and knowledge over various scientific findings. These solutions are pivotal tools in Amgens goal to accelerate the speed of discovery, and speed to market of advanced precision medications. Basic Qualifications: Masters degree and 1 to 3 years of Data Engineering experience OR Bachelors degree and 3 to 5 years of Data Engineering experience OR Diploma and 7 to 9 years of Data Engineering experience Must-Have Skills: Minimum of 3 years of hands-on experience with BI solutions (Preferable Power BI or Business Objects) including report development, dashboard creation, and optimization. Minimum of 3 years of hands-on experience building Change-data-capture (CDC) ETL pipelines, data warehouse design and build, and enterprise-level data management. Hands-on experience with Databricks, including data engineering, optimization, and analytics workloads. Deep understanding of Power BI, including model design, DAX, and Power Query. Proven experience designing and implementing data mastering solutions and data governance frameworks. Expertise in cloud platforms (AWS), data lakes, and data warehouses. Strong knowledge of ETL processes, data pipelines, and integration technologies. Good communication and collaboration skills to work with cross-functional teams and senior leadership. Ability to assess business needs and design solutions that align with organizational goals. Exceptional hands-on capabilities with data profiling, data transformation, data mastering Success in mentoring and training team members Good-to-Have Skills: Experience in developing differentiated and deliverable solutions Experience with human data, ideally human healthcare data Familiarity with laboratory testing, patient data from clinical care, HL7, FHIR, and/or clinical trial data management Professional Certifications: ITIL Foundation or other relevant certifications (preferred) SAFe Agile Practitioner (6.0) Microsoft Certified: Data Analyst Associate (Power BI) or related certification. Databricks Certified Professional or similar certification. Soft Skills: Excellent analytical and troubleshooting skills Deep intellectual curiosity The highest degree of initiative and self-motivation Strong verbal and written communication skills, including presentation to varied audiences of complex technical/business topics Confidence technical leader Ability to work effectively with global, remote teams, specifically including using of tools and artifacts to assure clear and efficient collaboration across time zones Ability to handle multiple priorities successfully Team-oriented, with a focus on achieving team goals Strong problem solving, analytical skills; Ability to learn quickly and retain and synthesize complex information from diverse sources

Job Description: We are looking for a Senior RTL Design Engineer with solid experience in ASIC Digital Design . The ideal candidate should possess strong expertise in RTL design using Verilog/System Verilog , with a proven background in developing complex digital designs and working on high-speed interfaces. This is a pure design-focused role ; candidates with FPGA-centric experience will not be considered . Key Responsibilities: Develop and implement RTL designs using Verilog/System Verilog . Work on SoC and IP-level designs focused on high-speed interfaces (e.g., APB, AXI, AHB, DDR, PCIe). Perform lint , CDC , RDC checks and validate timing constraints. Support post-silicon validation . Use EDA tools for simulation, synthesis, and timing analysis. Required Qualifications: Minimum 8 years of hands-on experience in ASIC RTL/Digital Design . Strong expertise in Verilog and System Verilog . Working knowledge of high-speed bus protocols: APB, AXI, AHB, DDR, PCIe . Proficient with industry-standard EDA tools . Good understanding and experience with static checks . Must have experience in ASIC Design only FPGA-focused candidates will not be considered . Interested Candidates share your resumes to priya@maxvytech.com

• 3+ years of solid experience in IP/SoC design • Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts • Good knowledge of Digital Design and RTL development • Hands-on experience with SoC Design, Verilog RTL coding • Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug • Working knowledge of Lint, CDC, PLDRC, CLP etc • Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification • Manage SoC dependencies, planning and tracking of all front-end design related tasks • Working for successful design delivery for the project milestones across the design, verification and physical implementations • Should possess effective communication skills Interested candidates can share their resumes to shubhanshi@incise.in

Create and support innovative Design Methodologies by leveraging feedback from our EDA and Digital IP teams. Integrate Methodologies into the development infrastructures of the Digital IP teams and demonstrate successful results. Support and maintain our regression infrastructure to manage changes and revise methodologies regularly. Test a range of Digital IPs through our Methodologies centered around Synopsys EDA tools. Collaborate with various teams to improve methodologies, enhancing both team and customer experiences. Develop and manage infrastructures, processes, methodologies, and checklists for the SG Digital IP Controllers. The Impact You Will Have: Enhance the efficiency and effectiveness of Digital IP development processes. Ensure high-quality and robust Digital IP products through rigorous methodology testing. Improve customer satisfaction by delivering superior Digital IP solutions. Drive innovation in design methodologies, contributing to Synopsys leadership in the industry. Facilitate seamless integration of methodologies into development infrastructures, optimizing workflows. Support the continuous improvement of regression infrastructures, ensuring up-to-date methodologies. What You'll Need: Bachelor's or Master's degree in electronics or electrical engineering or equivalent from reputed universities. 6-10 years of relevant experience in ASIC/SoC/IP Methodology. Proficiency in Synopsys implementation and infrastructure tools (coreConsultant, coreAssembler, SpyGlass/VC-SpyGlass, Fusion Compiler/Design Compiler, Prime Time, Formality, TestMax Manager, TCM, Verdi, VCS). Familiarity with multi-clock designs and understanding of Clock-Domain-Crossing principles. Proficiency in scripting languages (TCL, Perl, Python).

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering