187 Cdc Jobs - Page 3

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Join Qualcomms Wireless IP team to design and develop cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. You will work on high-performance, low-power digital designs across the full VLSI development cycle"”from architecture and micro-architecture to RTL implementation and SoC integration. This role offers the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Key Responsibilities Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design convergence. Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. Analyze and optimize for performance, area, and power. Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. Conduct CDC and lint checks using tools like Spyglass and resolve waivers. Participate in post-silicon debug and bring-up activities. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Skills & Experience 2"“15 years of experience in digital front-end ASIC/RTL design. Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable. Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. Experience with wireless modem IPs or similar high-performance digital blocks is a plus. Familiarity with low-power design methodologies and CDC handling. Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. Exposure to post-silicon debug and SoC integration challenges. Strong documentation and communication skills. Self-motivated with a collaborative mindset and ability to work with minimal supervision. Minimum Qualifications Bachelors or Masters degree in Electronics, VLSI, Communications, or related field. Proven experience in RTL design and SoC development. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 5+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As an ETL Developer for the Data and Analytics team, at Guidewire you will participate and collaborate with our customers and SI Partners who are adopting our Guidewire Data Platform as the centerpiece of their data foundation. You will facilitate and be an active developer when necessary to operationalize the realization of the agreed upon ETL Architecture goals of our customers adhering to Guidewire best practices and standards. You will work with our customers, partners, and other Guidewire team members to deliver successful data transformation initiatives. You will utilize best practices for design, development, and delivery of customer projects. You will share knowledge with the wider Guidewire Data and Analytics team to enable predictable project outcomes and emerge as a leader in our thriving data practice. One of our principles is to have fun while we deliver, so this role will need to keep the delivery process fun and engaging for the team in collaboration with the broader organization. Given the dynamic nature of the work in the Data and Analytics team, we are looking for decisive, highly-skilled technical problem solvers who are self-motivated and take proactive actions for the benefit of our customers and ensure that they succeed in their journey to Guidewire Cloud Platform. You will collaborate closely with teams located around the world and adhere to our core values Integrity, Collegiality, and Rationality. Key Responsibilities: Build out technical processes from specifications provided in High Level Design and data specifications documents. Integrate test and validation processes and methods into every step of the development process Work with Lead Architects and provide inputs into defining user stories, scope, acceptance criteria and estimates. Systematic problem-solving approach, coupled with a sense of ownership and drive Ability to work independently in a fast-paced Agile environment Actively contribute to the knowledge base from every project you are assigned to. Qualifications: Bachelors or Master’s Degree in Computer Science, or equivalent level of demonstrable professional competency, and 3 - 5 years + in a technical capacity building out complex ETL Data Integration frameworks. 3+ years of Experience with data processing and ETL (Extract, Transform, Load) and ELT (Extract, Load, and Transform) concepts. Experience with ADF or AWS Glue, Spark/Scala, GDP, CDC, ETL Data Integration, Experience working with relational and/or NoSQL databases Experience working with different cloud platforms (such as AWS, Azure, Snowflake, Google Cloud, etc.) Ability to work independently and within a team. Nice to have: Insurance industry experience Experience with ADF or AWS Glue Experience with the Azure data factory, Spark/Scala Experience with the Guidewire Data Platform.

Role Overview Seeking a highly skilled Kafka Developer with deep expertise in Kafka KSQL Streams-based transformations and hands-on experience working with Oracle, MS SQL, and PostgreSQL databasesespecially in environments with non-standard schemas (e.g., tables without primary keys, with/without constraints, and foreign keys). The ideal candidate will be responsible for designing and implementing scalable, real-time data pipelines and ensuring robust CDC (Change Data Capture) mechanisms for incremental data replication. Key Responsibilities • Design and implement Kafka Streams and KSQL-based transformations for real-time data processing. • Develop and maintain CDC pipelines using Kafka Connect, Debezium, or custom connectors. • Handle initial data loads from large relational datasets via manual exports and ensure seamless transition to incremental CDC. • Work with complex relational schemas , including: • Tables without primary keys • Tables with/without constraints • Foreign key relationships • Optimize data ingestion and transformation pipelines for performance, reliability, and scalability . • Collaborate with data architects, DBAs, and application teams to ensure data integrity and consistency. • Document technical designs, data flow diagrams, and operational procedures. • Communicate effectively with cross-functional teams and stakeholders. Required Skills and Experience • Strong hands-on experience with Apache Kafka , Kafka Streams , and KSQL . • Proficiency in Kafka Connect and CDC tools (Debezium, Confluent). • Deep understanding of Oracle, MS SQL Server, and PostgreSQL internals and schema design. • Experience handling non-standard table structures and resolving challenges in CDC replication. • Familiarity with manual data export/import strategies and their integration into streaming pipelines. • Strong knowledge of data serialization formats (Avro, JSON, Protobuf). • Proficient in Java or Scala for custom Kafka development. • Excellent communication skills —both written and verbal. Preferred Qualifications • Experience with schema registry , data governance , and data quality frameworks . • Familiarity with CI/CD pipelines , GitOps , and containerized deployments (Docker, Kubernetes). • Prior experience in data architecture or data platform engineering roles.

Mandatory Skills: ASIC Design Primary Skills:RTL, Coding, Design, IP Design, SOC Development, Lint, CDC, Micro Architecture Experience in: PCIe/DDR/Ethernet Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium Make flow, Perl, Shell, Python I2C, UART/SPI

Hiring now Criteria - B.Tech below 2022 and M.Tech below 2024 Location - Bangalore Preferred Engineers who have completed their Training in #VLSI domains for below requirements #PD #AL #RTL #DFT Share profiles to kartikchandu@juntrantech.com Health insurance Provident fund

Design, develop, and implement machine learning models and statistical algorithms.Analyze large datasets to extract meaningful insights and trends.Collaborate with stakeholders to define business problems and deliver data-driven solutions.Optimize and scale machine learning models for production environments.Present analytical findings and recommendations in a clear, actionable manner.Key Skills:Proficiency in Python, R, and SQL.Experience with ML libraries like TensorFlow, PyTorch, or Scikit-learn.Strong knowledge of statistical methods and data visualization tools.Excellent problem-solving and storytelling skills

Job Title: RTL Design Engineer Work Mode: Hybrid Location: Noida Job Description • Work together with system architects and micro architects to define high level specifications that are implementable. • Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks • Work closely with functional verification teams on test-plan development and debug. • Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. • UPF writing, power aware equivalence checks and low power checks. • Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. • Provide support to functional validation teams in post silicon debug. Qualifications • MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. • Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low- power checks, etc.), synthesis/DFT/FV/STA • Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. • Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. • Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. • Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. • Experience with post-silicon bring-up and debug is a plus. • Able to work with teams across the globe and possess good communication skills

Qualcomm India Private Limited is seeking a Software Engineer with expertise in various aspects of System on Chip (SoC) architecture and design. In this role, you will be responsible for working with AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. An understanding of Memory controller designs and microprocessors is considered an added advantage for this position. As a Software Engineer at Qualcomm, you will be required to have hands-on experience in constraint development and timing closure. Additionally, you will collaborate closely with the SoC verification and validation teams for pre/post Silicon debug. Proficiency in Low power SoC design, Synthesis, Multi Clock designs, and Asynchronous interface is crucial for this role. Experience in using tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is also a requirement. The ideal candidate for this position should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, along with at least 2 years of Software Engineering experience. Alternatively, a Master's degree with 1+ year of relevant work experience or a PhD in a related field is also acceptable. A minimum of 2 years of academic or work experience with Programming Languages like C, C++, Java, Python, etc., is necessary for this role. Qualcomm is an equal opportunity employer that is committed to providing an accessible process for individuals with disabilities who may need accommodations during the application/hiring process. If you require an accommodation, you may contact Qualcomm through the provided email address or toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For any inquiries about this role, please contact Qualcomm Careers directly.,

Overview The Tech Strategy & Enterprise Solutions Consumer Capability at PepsiCo drives personalization at scale by leveraging best-in-class technology stack. The team elevates consumer engagement through Salesforce Marketing Cloud, Data Cloud, MCP, and Service Cloud, enabling targeted campaigns and loyalty initiatives. Responsibilities Collaborate with cross-functional teams, including Business Analysts, Product Owners, and IT teams, to deeply understand Salesforce functionalities, assess risks, and develop robust solutions aligned with business requirements. Govern and maintain compliance with standards, including ISO and CMMI, to ensure alignment with organizational goals. Document solutions with a meticulous and detail-oriented approach, clearly articulating the how and why to build a comprehensive and accessible knowledge base. Act as the SPOC for Salesforce-related queries, ensuring timely and effective resolution. Manage user accounts, security settings, and data tasks such as imports, exports, and cleansing. Customize and maintain Salesforce objects, workflows, dashboards, and reports while ensuring usability and scalability. Monitor system performance, troubleshoot issues, and integrate Salesforce with third-party tools. Qualifications Mandatory Technical Skills Expertise in Salesforce administration, including custom objects, sharing settings, profiles, role hierarchies, Salesforce Shield, and GDPR compliance for secure system management. Proficiency in understanding the Salesforce Data Cloud elated metadata and working Proficiency in Salesforce reporting, analytics, and data visualization tools for decision-making. Familiarity with risk assessment frameworks for system development. Salesforce DataCloud Consultant (required) Salesforce Administrator Certification (required); Advanced certifications like Salesforce Advanced Administrator and Platform App Builder are preferred. Mandatory Non-Technical Skills A keen eye for detail and a proactive approach to identifying issues and inefficiencies. Strong problem-solving skills with the ability to develop and implement long-term solutions. A governance-focused mindset with a commitment to maintaining high operational standards. Effective communication and interpersonal skills to act as a trusted SPOC for stakeholders.

Role: Kafka Developer Exp: 5+ Years Location: Hyderabad Work Mode: Hybrid Work Type: C2H Date of Join: Immediate to 15days Role Overview Seeking a highly skilled Kafka Developer with deep expertise in Kafka KSQL Streams-based transformations and hands-on experience working with Oracle, MS SQL, and PostgreSQL databasesespecially in environments with non-standard schemas (e.g., tables without primary keys, with/without constraints, and foreign keys). The ideal candidate will be responsible for designing and implementing scalable, real-time data pipelines and ensuring robust CDC (Change Data Capture) mechanisms for incremental data replication. Key Responsibilities Design and implement Kafka Streams and KSQL-based transformations for real-time data processing. Develop and maintain CDC pipelines using Kafka Connect, Debezium, or custom connectors. Handle initial data loads from large relational datasets via manual exports and ensure seamless transition to incremental CDC. Work with complex relational schemas, including: Tables without primary keyso Tables with/without constraintso Foreign key relationships Optimize data ingestion and transformation pipelines for performance, reliability, and scalability. Collaborate with data architects, DBAs, and application teams to ensure data integrity and consistency. Document technical designs, data flow diagrams, and operational procedures. Communicate effectively with cross-functional teams and stakeholders. Required Skills and Experience Strong hands-on experience with Apache Kafka, Kafka Streams, and KSQL . Proficiency in Kafka Connect and CDC tools (Debezium, Confluent). Deep understanding of Oracle, MS SQL Server, and PostgreSQL internals and schema design. Experience handling non-standard table structures and resolving challenges in CDC replication. Familiarity with manual data export/import strategies and their integration into streaming pipelines. Strong knowledge of data serialization formats (Avro, JSON, Protobuf). Proficient in Java or Scala for custom Kafka development. Excellent communication skills both written and verbal. Preferred Qualifications Experience with schema registry, data governance, and data quality frameworks. Familiarity with CI/CD pipelines, GitOps , and containerized deployments (Docker, Kubernetes). Prior experience in data architecture or data platform engineering roles. Thanks & Regards, Sateesh Kumar Bavanasi NeuroGaint Systems Associate TA Phone: +91 6302059479 Email: sateeshkumar.bavanasi@ngsgeo.com URL: www.neurogaint.com

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus" AMD (Dont Share AMD Profiles) Preferred candidate profile

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Perl, along with experience in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). An understanding of performance design DFT techniques, end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), as well as the ability to scale DFT will be advantageous. Joining our team means being part of a group that continually pushes boundaries, focusing on developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation that underpins products adored by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering unmatched performance, efficiency, and integration. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our collaborative team leverages the best of Google AI, Software, and Hardware to create exceptionally helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to enhance people's lives through technology. In this role, your responsibilities will include collaborating with a team focusing on Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, and Static Timing Analysis (STA) checks. You will be tasked with writing a Pattern delivery using Automatic Test Pattern Generation (ATPG), contributing to Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns, as well as performing Silicon data analysis.,

Core Qualifications 12+ years in software/data architecture with hands on experience. Agentic AI & AWS Bedrock (MustHave): Demonstrated handson design, deployment, and operational experience with Agentic AI solutions leveraging AWS Bedrock and AWS Bedrock Agents . Deep expertise in cloud-native architectures on AWS (compute, storage, networking, security). Proven track record defining technology stacks across microservices, event streaming, and modern data platforms (e.g., Snowflake, Databricks). Proficiency with CI/CD and IaC (Azure DevOps, Terraform). Strong knowledge of data modeling, API design (REST/GraphQL), and integration patterns (ETL/ELT, CDC, messaging). Excellent communication and stakeholder-management skillsable to translate complex tech into business value. Preferred Media or broadcasting industry experience. Familiarity with Salesforce, or other enterprise iPaaS solutions. Certifications: AWS/Azure/GCP Architect , Salesforce Integration Architect , TOGAF . Mandatory Skills: Generative AI.

As the Cloud Network Subject Matter Expert (SME) at our organization, you will play a critical role in managing network architecture across cloud and on-premise infrastructure. With over 15 years of experience, including at least 10 years in network architecture leadership and 5 years as a cloud network architect, you will be responsible for executing enterprise-scale projects related to data strategy, cloud-based data lakes, API integration, SDWAN, and multi-cloud environments. Your primary focus will be on providing technical expertise in network and enterprise architecture, particularly from a cloud architect's perspective. This will involve leading enterprise-wide network initiatives, conducting architecture reviews, strategic planning, and addressing network issues proactively. You will also collaborate with various teams including Cloud operation teams, DevOps team, and other cross-functional project teams. In addition to your network architecture responsibilities, you will also act as a Cloud Consultant, offering guidance on complex solutions and technical architectural designs. Your role will involve implementing small to large-scale engagements, providing problem-solving approaches for dynamic challenges, and ensuring the alignment of solution strategies with business objectives. Key Result Areas (KRAs) for this role include project and delivery management, solution architecture, systems integration, risk management, team management, and compliance with industry standards. You will be expected to have hands-on experience in managing enterprise-scale on-premise and cloud networks, familiarity with routing protocols such as OSPF, BGP, RIP, EGP, IGP, and expertise in Azure services and other public cloud solutions. To excel in this role, you should hold a B.E. degree, with additional certifications like CCNP, CCNA, Azure/AWS network certifications, TOGAF, and Microsoft Azure certifications being desirable. Your ability to lead technical troubleshooting, design network architectures, and provide expert guidance to business teams will be essential in driving the organization's IT strategy and competitive advantage. If you are passionate about network architecture, cloud solutions, and driving innovation in a dynamic environment, we invite you to join our team as the Cloud Network SME in Mumbai. Your expertise and leadership will be instrumental in shaping the future of our network infrastructure and cloud services. (Note: This Job Description is a summary based on the provided information and may require further customization as per organizational needs.),

We are actively hiring multiple Design Verification (DV) Engineers for Bangalore (hybrid model). If youre looking for a new challenge and can join quickly, youll be among our top-priority candidates! Open Positions : 1. DV Engineer GLS / UVM / SystemVerilog / CDC Experience : 3–8 years Skills : Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification 2. DV Engineer – PCIe / DDR / UVM / SV Experience : 4–18 years Skills : Protocol-level verification, PCIe or DDR, UVM, SystemVerilog 3. DV Engineer – UVM / SystemVerilog Experience : 5–10 years Skills : Testbench architecture, functional verification, scalable UVM environments

Front End Integration of Digital, Analog IPs and Subsystems to build complete SoC Netlist. IOMUX and Padring generation and integration. Design of SoC Specific Logic IPs. Perform quality checks like Lint and CDC at SoC level. Implement all feedback from Verification and Physical Design teams for all changes required. Develop SoC level Testbench for RTL and Postlayout Simulations. Collaborate with ATE and Test teams and deliver test patterns for Probe and Package level testing. Support Verification and Post-Silicon Debugging of issues. Experience and Skills Required 10-15 Years Experience in front end integration for complex SoCs. Strong scripting skills. Hands on experience in RTL coding, Lint, CDC. Experience in developing IOMUX and Padring. Expertise in developing testbench for SoC to support directed and random verification. Experienced with working with ATE teams for delivery of test patterns. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Development of Specifications, Micro Architecture, RTL Development for Digital IPs. Setup and use standard EDA tools for Verification, Lint CDC, Synthesis, Power Analysis tools for Verification and Ensuring PPA for IP developed. Conduct Reviews for Documentation, RTL and Verification Tests. Experience and Skills Required 5 to 15 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, verification and debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Job Title: SoC Design lead/manager Expectation: 12+ Years of relevant industry experience in multiple SoC designs Strong technical background in driving SoC design independently Experience in processor system integration, NoC design and integration, Good understanding of high-speed protocols such as PCIe/DDR/HBM/Ethernet etc.. Strong experience with AXI/AHB bus protocols. Defining sign-off quality design constraints for SoC. Hands-on expertise with low-power design techniques such as UPF/CPF. Experience in Security aspects in SoC [secure JTAG, encryption/decryption] &secure boot design. Experience in Lint/CDC checks Hand-on experience in Verilog HDL, System Verilog, C/C++ Drive one or more teams for their respective deliverables. Ensure the quality of deliverables and take necessary steps to improve the quality Excellent analytical and problem-solving skills. Excellent communication skills to interact with cross-functional teams to build consensus. Good teamwork spirit and collaboration skills with team members. Education BTech or MTech or equivalent experience in Electronics Engineering.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques. Experience with a scripting language such as Perl or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. Experience implementing image/video processing blocks or other multimedia IPs such as Display or ISP Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for clock domain checks and reset checks Experience in scripting languages, C/C++ programming and software design skills. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes Micro architecture, RTL coding, definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for quality and optimized security designs. You will be involved in Micro-Arch and RTL coding for imaging and video codecs - IPs and subsystems. You will also contribute to improvements by debugging and by using different RTL QC tools like Lint, CDC, VCLP. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis. Develop RTL implementations that meet competitive power, performance and area targets. Participate in synthesis, timing/power closure and Field-Programmable Gate Array (FPGA) or silicon bring-up. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture or micro-architecture planning. ,

We are looking for a highly motivated and experienced AWS Engineer who possesses AWS cloud experience and a strong desire to stay updated on the latest cloud development best practices. As an AWS Engineer, your primary responsibility will be to identify requirements and develop top-notch cloud-native solutions that are repeatable, scalable, and well-governed. You will be tasked with deploying and thoroughly testing solutions to ensure their robustness and security. Additionally, you will be accountable for creating and managing diagrams related to the solutions deployed in production. Key Requirements: - Designing and developing RESTful services. - Building serverless applications in AWS. - Constructing real-time/streaming data pipelines. - 3-4 years of SQL & Python programming experience. - 2-3 years of experience with various AWS technologies such as Glue, Redshift, Kinesis, Athena, CloudTrail, CloudWatch, Lambda, API Gateway, Step functions, SQS, S3, IAM roles, Secrets Manager. - Proficiency in ETL Tools like Glue, Fivetran, Talend, Matillion, etc. - 1-2 years of experience in DBT with Data Modeling, SQL, Jinja templating, and packages/macros for building robust data transformation pipelines. - Experience with Airbyte for building ingestion modules and CDC mechanisms. - Hands-on experience in distributed architecture systems handling large data volumes. - Strong problem-solving skills and ability to work independently. - Knowledge of Big Data Design Patterns, NoSQL databases, and cloud-based data transformation technologies. - Understanding of object-oriented design principles and enterprise integration patterns. - Familiarity with messaging middleware and building cloud-based applications. - Strong collaboration, communication, and self-driven work ethic. - Proficient in writing clean and effective code. Preferred Skills: - AWS Cloud Certifications. - Experience with Airflow, MWAA, Jinja templating in Python. - Knowledge of DevOps methodologies and CI/CD pipeline design. - Familiarity with Pyspark, DevOps, SQL, Python, and PySpark. - Experience in building Real-Time streaming data pipelines with Kafka, Kinesis. - Understanding of Data warehousing, Data Lake solutions, and Azure DE. - Ability to create and maintain scalable AWS architecture. - Collaboration with technical teams on modern architectures like Microservices, REST APIs, DynamoDB, Lambda, API Gateway. - Developing API-based, CDC, batch, and real-time data pipelines for structured and unstructured datasets. - Integration with third-party systems, ensuring repeatability and scalability. - Gathering requirements, developing solutions, and deploying them with development teams. - Providing comprehensive solution documentation and collaborating with data professionals. - Prioritizing data protection and cloud security in all aspects. If you do not meet all the requirements listed but believe you have unique skills to offer, we encourage you to apply for this role as there may be a suitable opportunity for you in the future.,

Job Title: Principal Software Engineer This is a permanent full-time role with an option to work from home. However, if you are shortlisted - you must come down to Vadodara (office) for the first 5 days before going back. Your travel and accommodation will be provided by the company. Summary: The Principal Software Engineer is responsible for designing, developing, and maintaining high-quality software products that align with business requirements and exceed customer expectations. As a key member of the development team, this role involves close collaboration with product management, QA teams, and other stakeholders to drive a robust development process supporting the company's growth objectives. The ideal candidate will bring extensive expertise in full-stack software development, strong problem-solving skills, and the ability to effectively communicate and collaborate across cross-functional teams. Exp 12+ yrs CTC up to 30 LPA Notice period: 0-15 days No of open requirements - 3 Must have skills: C# .NET 8+ Angular (Please mention the latest version you worked on in the comment section) HTML, CSS & JavaScript NgRx Web API SQL Server GIT Hangfire Cloud Services Azure Service Bus JIRA CI/CD Design Patterns Microservices Elastic Search CDC Job Types: Full-time, Permanent Pay: 1,500,000.00 - 3,000,000.00 per year Benefits: Health insurance Provident Fund Work from home Schedule: Day shift Fixed shift Monday to Friday Morning shift UK shift Supplemental Pay: Yearly bonus Application Question(s): Must have experience with Azure (Bus), .NET Core 8, Angular (At least 4 years), Microservices, and have overall 12+ years of experience and be able to onboard in 0-15 days. This is a remote role - but if you are selected, you must come down for the first 5 days before going back. Travel and hotel stay will be provided. Work Location: Remote

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 4 to 7 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Skills & Experience MTech/BTech in EE/CS with 7+ years of ASIC design experience. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage. Understanding of protocols like AHB/AXI/ACE/CHI is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Hands on experience in Low power SoC design is required. Responsibilities Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules. Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. Hands on experience in constraint development and timing closure. UPF writing, power aware equivalence checks and low power checks. Support performance debugs and address performance bottle necks. Provide support to sub-system, SoC integration and chip level debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 8+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for complex Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions.