53 Cadence Tools Jobs - Page 2

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: ...

Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are seeking a highly skilled and motivated STA (Static Timing Analysis) Engineer to join our team specializing in timing analysis for cutting-edge and complex SoC projects. This role offers a unique opportunity to work on high-level designs and collaborate with multidisciplinary teams in a dynamic and challenging environment. Your Responsibilities May Include But Not Be Limited To STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Tim...

Job Description: Analog layout designer providing onsite support for advanced nodes, working with global layout and design team. Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout. Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc. Should have worked on and top-level integration Should have a good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, preference will be given to FinFet experience candidates. Should have a g...

Role Overview: Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to mak...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. We are seeking a Principal Digital Design Engineer with deep expertise in high-performance controller an...

We are looking for highly experienced Senior ASIC Engineers to lead and contribute to complex ASIC projects. This role requires expertise in advanced physical design, verification, and tapeout processes. The ideal candidate will have a proven track record of delivering high-quality ASIC designs in advanced technology nodes. Responsibilities: Lead and execute complex physical design implementations, including block-level low power aware floorplanning, placement, CTS, routing, RC extraction, STA, IR/EM analysis, and DRC/LVS/ERC. Manage hierarchical physical verification and signoff closures. Develop and implement advanced UVM verification environments for IP and full-chip verification. Verify ...

As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and ...

Role Overview: As a Hardware Engineering Intern at Google, you will be part of a team shaping the future of Google Cloud Silicon, including TPUs, Arm-based servers, and network products. You will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon. Your responsibilities will be dynamic and multi-faceted, focusing on product definition, design, and implementation. You will work closely with Engineering teams to achieve the optimal balance between performance, power, features, schedule, and cost. Key Responsibilities: - Work with hardware and software architects and designers to architect, model, analyze...

The company offers a comprehensive portfolio of Multi-phase voltage regulators catering to various market segments such as Intel Server, AMD servers, personal electronics, and automotive. As a part of the Power Stage development team, you will be involved in the complete product development lifecycle, from definition to product release. The team takes pride in fostering innovation and converting these innovative ideas into products within customer-driven timelines. Your responsibilities in this role will include developing a coverage-driven verification plan in collaboration with the System, APPS, and design teams to ensure the success of silicon in the first pass. You will be responsible fo...

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing...

As an Engineer (DFT) at eInfochips located in Bangalore, India, you will be responsible for hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in the usage of Synopsys tools such as DFT MAX and TetraMAX, as well as Cadence tools like RTL Compiler, Encounter Test, modus, and Janus. Additionally, experience with Mentor Graphics tools like Tessent tool chain, TestKompress, Debussy, VCS/Questa/IUS, and PT tool from Synopsys will be advantageous. This is a full-time position falling under the category of Engineering Services.,

At Cadence, we are dedicated to hiring and nurturing leaders and innovators who are passionate about making a difference in the technology sector. As part of the CIC Frontend team in the role of AE3, you will have the opportunity to engage with customers and prospects, identify and assess opportunities, establish evaluation criteria, conduct evaluations, and successfully convert opportunities into business deals that lead to the implementation of efficient circuit simulation and mixed-signal methodologies using Cadence tools. A key aspect of this role is to have a deep understanding of customer processes and challenges, coupled with strong analytical skills to overcome issues that may impact...

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require ins...

As a Lead Physical Design Engineer, you will be responsible for leveraging your expertise in 65nm and above technologies (specifically 180nm) to work on DC-DC converters, buck boost converters, LDOs, Op-Amps, and Blocks. Your role will involve collaborating on Digital blocks within AMS projects (NXP/TI) rather than purely Digital projects (like AMD/Intel). It is essential that you have experience working on higher nodes such as 140nm, 180nm, 190nm, etc. Understanding Digital basics like DFF (D Flipflop) functionality is required, covering the fundamental aspects. Proficiency in Cadence tools is a must, along with knowledge of DFT insertion and hands-on experience with full chip tape out. You...

You will be joining the global AMS team, which is responsible for the development of high-performance Mixed Signal blocks. The team oversees the physical implementation and integration of the blocks in the IC. Additionally, the team is involved in validation and collaborates closely with Architects and Application Engineers to derive Specs. As a member of the team, your responsibilities will include defining architecture and implementing transistor-level design of analog and mixed-signal blocks for Power efficient IoT ICs. You will also drive system-level specification and partitioning in collaboration with Systems and Application teams. Performing pre- and post-layout simulations and analys...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.? Renesas employs roughly 21,000 people in more than 30 countries worldwid...

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis,...

Job description Job Description The Foundation IP Corporate Memory Organization is looking for an experienced Memory Layout Designer to join its team. Develop custom layout design for memory compilers (e.g., bit cells, SRAMs, Register Files). Perform detailed physical array planning, area optimization, critical wire analysis, and custom leaf cell layout. Conduct complete layout verification including design rule compliance, electromigration, voltage drop (IR), selfheat, and other reliability checks. May use custom autorouters and custom placers to efficiently construct layout. Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement r...

You are an experienced AMS Verification Engineer with over 8 years of expertise in AMS IC verification, possessing hands-on experience in VerilogAMS, SystemVerilog, and UVM. Your strong skills lie in VerilogAMS and Real Number Modeling, and you have a solid understanding of Cadence tools, VManager, and Tcl/Perl. Any knowledge or experience in Analog/RF would be considered a valuable advantage. The location for this position is in Bengaluru. If you believe you are a suitable candidate for this role, we encourage you to reach out by either sending a direct message or sharing your CV to aayushi.sharma@saracasolutions.com. Join us in shaping the future of semiconductors!,

As a Design Engineer - II at TekWissen Group in Noida, you will be responsible for hardware board design in a customer-centric information technology environment. You should possess a Bachelor's degree in electronics, product & industrial design, or a related field, with a Master's degree considered a plus. With a minimum of 8+ years of experience in hardware board design or a similar manufacturing environment, you are expected to have a solid understanding of the manufacturing process, quality requirements, and DFM process. Your role will require expertise in high-speed digital signal design and testing, as well as a thorough understanding of electronics components. Proficiency in Cadence t...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . We are seeking a Senior Digital Design Engineer w...

As part of the custom product business at our company, you will be contributing to the development of industry-leading custom IC system solutions across various product categories such as display and touch power products, camera PMICs, charger power products, power switches/muxes, Laser drivers, and high-speed communication interfaces. By integrating signal chain and power components, your work will play a key role in enabling our customers to enhance their next-gen products in the personal electronics domain. Joining our team presents a unique opportunity to be part of a world-class custom semiconductor team. Your responsibilities in this role will include verifying complex analog designs/s...

Experience: 5 + Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills Skills ...

Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills