Senior Mixed Signal Verification Engineer

The company offers a comprehensive portfolio of Multi-phase voltage regulators catering to various market segments such as Intel Server, AMD servers, personal electronics, and automotive. As a part of the Power Stage development team, you will be involved in the complete product development lifecycle, from definition to product release. The team takes pride in fostering innovation and converting these innovative ideas into products within customer-driven timelines. Your responsibilities in this role will include developing a coverage-driven verification plan in collaboration with the System, APPS, and design teams to ensure the success of silicon in the first pass. You will be responsible for model development using RNM/EENET, creating test scenarios, automation, and generating stimulus to verify the design under test. Additionally, you will work on regression tools, develop scripts for regression analysis, and contribute to enhancing the quality and efficiency of the DV strategy, tools, methods, and flows. To be successful in this role, you are expected to have strong skills in Circuit Debug, experience in automation using Verilog AMS, and the ability to independently debug circuit issues and report them. Knowledge of System Verilog and proficiency in scripting languages such as Python and Perl are beneficial. Being a good team player with a positive attitude, a thirst for continuous learning, excellent communication skills, and the ability to work independently are also essential. Preferred qualifications for this role include 2-5 years of experience in Mixed Signal verification and proficiency in tools such as Virtuoso, Verilog, Verilog AMS, and Cadence tools like xrun/ncsim/Vmanager.,