Senior Mixed Signal Verification Engineer

In this role at TI, you will be responsible for developing a coverage driven verification plan by collaborating closely with System, APPS, and design teams to ensure the success of first pass silicon. You will also be involved in model development using RNM/EENET, creating test scenarios, automation, and stimulus to verify the design under test. Additionally, your role will include working with regression tools, developing scripts for regression analysis, and contributing to continuous improvements in quality and efficiency on DV strategy, tools, methods, and flows. Key Responsibilities: - Develop a coverage driven verification plan in collaboration with System, APPS, and design teams - Model development using RNM/EENET - Create test scenarios, automation, and stimulus for design verification - Utilize regression tools and develop scripts for regression analysis - Contribute to continuous improvements in quality and efficiency of DV strategy, tools, methods, and flows Qualifications Required: - Strong in Circuit Debug - Proficiency in automation using Verilog AMS - Ability to independently debug circuit issues and report them - Knowledge of System Verilog (added advantage) - Proficiency in Scripting languages such as Python, Perl, etc. - Good team player with a thirst for continuous learning - Strong communication and interpersonal skills - Ability to function independently In addition, the preferred skills/experience for this role include: - 2-5 years of experience in Mixed Signal verification - Skills in Virtuoso, Verilog, Verilog AMS, and Cadence tools like xrun/ncsim/Vmanager,