53 Cadence Tools Jobs

Role Overview: As a Physical Design Engineer at Texas Instruments Incorporated (TI), you will be a part of the Embedded Processor Group, focusing on Backend Signoff and Reliability. You will play a crucial role in the Power Grid planning and design at Chip level, utilizing hands-on experience in Innovus tool for custom routing to meet stringent integration requirements. Your responsibilities will also include Signal and Power bump planning and routing, as well as working on full chip EMIR, SigEM, and Cell EM. Additionally, you will be involved in Backend Signoff flows such as DRC, PERC, LVS, Latup-Up, ESD, and have hands-on experience in Cadence tools like Innovus, Voltus, Tempus, and Pegasu...

As a member of the team at Google, you will be involved in developing custom silicon solutions for Google's direct-to-consumer products. Your contribution will help in shaping the future hardware experiences, focusing on performance, efficiency, and integration. The Platforms and Devices team at Google is responsible for various computing software platforms and first-party devices that incorporate Google AI, software, and hardware, aiming to create innovative experiences for users globally. **Key Responsibilities:** - Use investigative and simulation techniques to ensure Performance, Power, and Area (PPA) meet defined requirements. - Collaborate with cross-functional teams to debug failures ...

As an experienced NoC Design Engineer specializing in RTL Design, you will be responsible for the following key tasks: - Utilize your expert knowledge in NoC microarchitecture to integrate configurations within multi-clock and multi-power domain-based SoCs. - Demonstrate extensive working knowledge of AXI, AHB, and APB bus protocols. - Perform RTL quality checks using tools like Lint, CDC, etc. - Display proficiency in System Verilog and VHDL, with a strong background in SoC/ASIC design flow. - Apply RTL synthesis knowledge and efficiently use Synopsys/Cadence tools. - Utilize industry-standard tools such as Modelsim, VCS for functional simulations. - Collaborate with verification teams to d...

In this role at TI, you will be responsible for developing a coverage driven verification plan by collaborating closely with System, APPS, and design teams to ensure the success of first pass silicon. You will also be involved in model development using RNM/EENET, creating test scenarios, automation, and stimulus to verify the design under test. Additionally, your role will include working with regression tools, developing scripts for regression analysis, and contributing to continuous improvements in quality and efficiency on DV strategy, tools, methods, and flows. Key Responsibilities: - Develop a coverage driven verification plan in collaboration with System, APPS, and design teams - Mode...

Job Requirements At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better placeto make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities Primary requirement is Need to have Cadence tools experience like: Genus, Innovus & Tempus. Should als...

Introduction About IBM IBM's greatest invention is the IBMer. We believe that progress is made through progressive thinking, progressive leadership, progressive policy and progressive action. IBMers believe that the application of intelligence, reason and science can improve business, society and the human condition. Restlessly reinventing since 1911, we are the largest technology and consulting employer in the world, with more than 380,000 IBMers serving clients in 170 countries. About Business Unit India Systems Development Lab (ISDL) is part of IBM Systems world-wide technology development lab. Established in 1996, the Lab is headquartered in India's Silicon Valley and startup hub - Benga...

Job Description: As an Engineer (DFT) at eInfochips in Bangalore, India, you will have hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in using Synopsys tools such as DFT MAX and TetraMAX, Cadence tools like RTL Compiler, Encounter Test, modus, Janus, as well as Mentor Graphics tools such as Tessent tool chain, TestKompress, Debussy, VCS, Questa, and IUS. Additionally, familiarity with PT tool from Synopsys will be advantageous. Key Responsibilities: - Hands-on experience in Scan insertion - Proficiency in MBIST and JTAG implementation - Expertise in ATPG and Patte...

Company Description Devika Sakhuja Designs specializes in creating stunning events that are produced and styled to perfection. We design, curate, and execute weddings globally, ranging from small intimate gatherings to large, lavish weddings. Our team balances old-world charm with modern aesthetics, keeping in mind the preferences of the bride, groom, and their families. We design bespoke, beautiful, and fun dcor elements that align with international trends to ensure each event is as unique as our clients and their vision. Role Description This is a full-time on-site role for a Senior Layout Designer located in New Delhi. The Senior Layout Designer will be responsible for designing and impl...

Role Overview: You are required to lead the end-to-end VLSI components and hardware systems, providing customer support and governance of VLSI components and hardware systems, and managing the team effectively. Key Responsibilities: - Design, analyze, develop, modify, and evaluate VLSI components and hardware systems - Determine architecture and logic design verification through software for component and system simulation - Conduct system evaluations, make appropriate recommendations, and review data and project documentation - Identify and recommend system improvements for better technical performance - Inspect VLSI components and hardware systems for compliance with regulations and safety...

As an experienced Layout Memory Engineer, your role will involve hands-on experience with important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. You should have a strong background in working with 16nm/14nm/10nm/7nm/Finfet process technologies and top-level memory integration, along with expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. Your responsibilities will also include addressing IR/EM related issues in memory layouts and utilizing Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A solid understanding of ultra-de...

Job Title: Digital Backend Design Engineer Location: Bangalore Experience: 610 Years Job Description We are seeking an experienced Digital Backend Design Engineer with strong hands-on expertise in digital backend design flows, physical verification, low-power methodologies, and scripting. The candidate will work with leading EDA tools from Cadence and Synopsys , contributing to complex digital design projects. Key Responsibilities Perform digital backend design using Cadence and Synopsys tools. Conduct physical verification using Mentor Calibre or Cadence PVS tools. Apply low-power design techniques and implement UPF methodology. Develop and maintain scripts in TCL, Shell, Perl, or Python to...

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About The Job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. JD for CIC Frontend req AE3 Your role will be to meet customers/prospects and identify & qualify the opportunities, work out agreeable and achievable evaluation criteria, run through the evaluation and convert the opportunities into business leading to deployment of an efficient circuit simulation and mixed signal methodology using Cadence tools. It requires a very good understanding of customer flow & challenges and a good analytical ability to resolve issues impacting production schedule. Handson knowledge / experience on analog and mixed-signal circuit Design / Debug / modeling an...

Role Overview: As a Layout Design Engineer, your main role will involve hands-on experience with layouts of important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in a compiler context. You should have worked on 16nm / 14nm / 10nm / 7nm / Finfet process technologies. Additionally, you should have hands-on experience with top-level memory integration and expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. A good handle on IR/EM related issues in memory layouts is also essential. Key Responsibilities: - Work on layouts of memory building blocks in a compiler context - Ensure top-level memory integr...

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities: ? Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. ? Perform Static Timing Analysis (STA) and ensure timing closure across all design corners. ? Execute power integrity and physical verification checks (LVS, DRC). ? Co...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with programming languages such as Perl, Python, or TCL. Experience in managing block physical implementation and Quality of Results (QoR). Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with computer architecture. Experience with constraints, synthesis or Clock Tree Synthesis (CTS)...

Experience: 10+ years Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Leading junior teams, Mentoring/Trainin...

As part of the Embedded Processors group of TI, you will be working with the Processors and Application Specific Microcontroller (ASM) Business Units. Your role will involve developing cutting-edge system-on-chips (SoCs) for microcontrollers and processors, including 5nm technologies, for industrial and automotive applications. The team is known for creating differentiated IPs with patented technologies that enhance ADAS, Zonal, Domain controller, and Real-Time Control application performance. Your responsibilities will include designing high-performance CPU cores, math co-processors, interconnects, networking and multimedia controllers, safety and security infrastructure, and control and co...

Role We are looking for a talented a R&D Hardware Engineer to design, develop, and validate electronic hardware for intelligent devices used in commercial building HVAC systems. This role involves working closely with cross-functional teams to deliver reliable, energy-efficient, and standards-compliant solutions for modern building automation. We are looking for a positive, confident, and self-motivated individual who thrives in a fast-paced, team-based environment and is passionate about developing next-generation technologies that connect and empower our products and customers. Responsibilities: Design analog and digital circuits for intelligent devices ranging from environmental sensor, p...

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file