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6.0 - 10.0 years

14 - 19 Lacs

Bengaluru

Hybrid

Naukri logo

Job Details: You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for power delivery network design, IR Drop analysis and convergence of complex core design. Your Responsibilities Will Include But Not Limited To Responsible for power delivery network design including package/bump to device level delivery for over 5GHz Freq and low-power digital designs. Deep understanding of RV and IR Drop concepts. Load line definition Closely work with SD, Integration and Floor plan teams Qualifications: * You must possess a master's degree in electrical or Electronics Engineering with at least 6 or more years of experience in related field or a bachelor's degree with at least 8 years of experience. * With a deep Technical Expertise On - power delivery network IR and RV analysis, MIM spread with Tools: Redhawk, RHSC Additional preferred Skills being. * Technical Expertise in Static Timing Analysis is preferred. * Preferred Additional Skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Shift: Shift 1 (India)

Posted 2 weeks ago

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6.0 - 8.0 years

25 - 40 Lacs

Bengaluru

Work from Office

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The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

Posted 3 weeks ago

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5 - 10 years

5 - 14 Lacs

Hyderabad

Work from Office

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We are looking for highly experienced Senior ASIC Engineers to lead and contribute to complex ASIC projects. This role requires expertise in advanced physical design, verification, and tapeout processes. The ideal candidate will have a proven track record of delivering high-quality ASIC designs in advanced technology nodes. Responsibilities: Lead and execute complex physical design implementations, including block-level low power aware floorplanning, placement, CTS, routing, RC extraction, STA, IR/EM analysis, and DRC/LVS/ERC. Manage hierarchical physical verification and signoff closures. Develop and implement advanced UVM verification environments for IP and full-chip verification. Verify complex high-speed protocols (SERDES, UNIPRO, PCIE, UFS, DDR). Drive STA closure at block and chip levels. Manage and contribute to tapeout activities, with experience in multiple tapeouts. Work with advanced process technology nodes (7nm, 6nm, 5nm). Utilize Cadence (Innovus, Tempus) and Mentor Caliber tools effectively. Guide and mentor junior engineers. Collaborate with global teams to ensure project success. Contribute to project planning, scheduling, and risk management. Develop and maintain comprehensive documentation. Required Skills: Extensive experience in physical design and verification. Expertise in advanced UVM verification methodologies. Strong understanding of high-speed protocols. Proven track record of successful tapeouts. Proficiency in Cadence and Mentor tools. Strong analytical and problem-solving skills. Excellent communication and leadership skills. Experience with advanced process technology nodes. Knowledge of digital electronics and microprocessors. Experience: 5+ years of relevant experience, with a preference for 7+ years.

Posted 2 months ago

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