20 Cadence Tools Jobs

Role Overview: As a Hardware Engineering Intern at Google, you will be part of a team shaping the future of Google Cloud Silicon, including TPUs, Arm-based servers, and network products. You will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon. Your responsibilities will be dynamic and multi-faceted, focusing on product definition, design, and implementation. You will work closely with Engineering teams to achieve the optimal balance between performance, power, features, schedule, and cost. Key Responsibilities: - Work with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon - Collaborate with Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost - Have responsibilities in areas such as product definition, design, and implementation - Contribute to shaping the future of Google Cloud Silicon, including TPUs, Arm-based servers, and network products Qualifications Required: - Currently pursuing a PhD degree in Computer Engineering, Computer Science, Electronics and Communication Engineering, Electrical Engineering, or a related technical field - Experience in Hardware System Integration, Signal and Power Integrity, System Validation, Wireless Communications, Product Design, Computer Architecture, Digital Design Verification, Digital Circuits, ASIC Physical Design, FPGAs, Embedded Systems, Memory Systems - Experience in programming languages such as C++, Python, Verilog, UVM, Synopsys, and Cadence tools - Experience with wireless communication interfaces and sensors - Experience with performance modeling tools, C++, Python, Silicon design tools in Front End/Design Verification/Physical Design - Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies, computer architecture, linear algebra, ML/DL background - Knowledge of high performance and low power design techniques - Currently attending a degree program in India and available to work full time for 12 weeks outside of university term time Additional details of the company: Google is an engineering company that prioritizes security, efficiency, and reliability. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services. Their end users are Googlers, Cloud customers, and people who use Google services around the world. The company focuses on developing the latest Cloud Si products and running a global network while driving towards shaping the future of hyperscale computing. Google engineers work on various technical challenges to make an impact on millions of users and revolutionize technology. (Note: The section "Additional details of the company" has been included based on the information provided in the job description),

The company offers a comprehensive portfolio of Multi-phase voltage regulators catering to various market segments such as Intel Server, AMD servers, personal electronics, and automotive. As a part of the Power Stage development team, you will be involved in the complete product development lifecycle, from definition to product release. The team takes pride in fostering innovation and converting these innovative ideas into products within customer-driven timelines. Your responsibilities in this role will include developing a coverage-driven verification plan in collaboration with the System, APPS, and design teams to ensure the success of silicon in the first pass. You will be responsible for model development using RNM/EENET, creating test scenarios, automation, and generating stimulus to verify the design under test. Additionally, you will work on regression tools, develop scripts for regression analysis, and contribute to enhancing the quality and efficiency of the DV strategy, tools, methods, and flows. To be successful in this role, you are expected to have strong skills in Circuit Debug, experience in automation using Verilog AMS, and the ability to independently debug circuit issues and report them. Knowledge of System Verilog and proficiency in scripting languages such as Python and Perl are beneficial. Being a good team player with a positive attitude, a thirst for continuous learning, excellent communication skills, and the ability to work independently are also essential. Preferred qualifications for this role include 2-5 years of experience in Mixed Signal verification and proficiency in tools such as Virtuoso, Verilog, Verilog AMS, and Cadence tools like xrun/ncsim/Vmanager.,

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. You should possess expertise in Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl/Tk/Perl and hands-on experience with Synopsys/Cadence tools (Innovus, ICC2, Primetime, PT-PX, Calibre) is essential. Additionally, you should be well-versed in timing constraints, STA, and timing closure. Your key duties will involve leading end-to-end VLSI components and hardware systems, providing customer support and governance of VLSI components and hardware systems, and managing a team. You will be responsible for resourcing, talent management, performance management, and employee satisfaction and engagement within your team. In terms of deliverables, you will be evaluated based on verification timeliness, quality, and coverage, compliance with UVM standards, customer responsiveness, project documentation and MIS generation, team training on new skills, team attrition percentage, and employee satisfaction score (ESAT). The mandatory skills required for this role include expertise in VLSI Physical Place and Route with 5-8 years of experience. If you are inspired by reinvention and are looking to evolve your career in a dynamic environment, Wipro offers the opportunity to be part of a modern, purpose-driven organization that empowers you to design your own reinvention. Join us at Wipro and realize your ambitions. Applications from individuals with disabilities are warmly welcomed.,

As an Engineer (DFT) at eInfochips located in Bangalore, India, you will be responsible for hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in the usage of Synopsys tools such as DFT MAX and TetraMAX, as well as Cadence tools like RTL Compiler, Encounter Test, modus, and Janus. Additionally, experience with Mentor Graphics tools like Tessent tool chain, TestKompress, Debussy, VCS/Questa/IUS, and PT tool from Synopsys will be advantageous. This is a full-time position falling under the category of Engineering Services.,

At Cadence, we are dedicated to hiring and nurturing leaders and innovators who are passionate about making a difference in the technology sector. As part of the CIC Frontend team in the role of AE3, you will have the opportunity to engage with customers and prospects, identify and assess opportunities, establish evaluation criteria, conduct evaluations, and successfully convert opportunities into business deals that lead to the implementation of efficient circuit simulation and mixed-signal methodologies using Cadence tools. A key aspect of this role is to have a deep understanding of customer processes and challenges, coupled with strong analytical skills to overcome issues that may impact production schedules. Hands-on experience in analog and mixed-signal circuit design, debugging, modeling, and simulation is considered advantageous. Collaboration with the Research and Development (R&D) and Product Engineering teams is essential for implementing new features and addressing any bugs that may arise. Given the significant customer interaction involved in issue resolution and identifying opportunities to expand the utilization of Cadence technologies, as well as the close coordination with R&D and other stakeholders, exceptional customer service, communication skills, and leadership qualities are indispensable for success in this role. The ideal candidate for this position must possess a comprehensive understanding of IC design processes and methodologies, particularly in analog and mixed-signal design. Proficiency in various tools such as Virtuoso Schematic, Virtuoso ADE, Spectre, AMS Designer, and expertise in the entire analog front-end flow from design entry to post layout simulation and analysis are prerequisites. A Bachelor's degree in Engineering (B.Tech or equivalent) with 3 to 7 years of relevant experience is required to excel in this role. Join us in our mission to tackle challenges that others find insurmountable and be part of a team that is truly making a difference in the world of technology.,

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require inspirational leadership, effective communication skills, and the ability to collaborate in a global environment. Overall, your responsibilities will revolve around ensuring the successful implementation of physical design tasks, adhering to project timelines, and maintaining high quality standards throughout the process. Your contributions will play a key role in the development of cutting-edge semiconductor products.,

As a Lead Physical Design Engineer, you will be responsible for leveraging your expertise in 65nm and above technologies (specifically 180nm) to work on DC-DC converters, buck boost converters, LDOs, Op-Amps, and Blocks. Your role will involve collaborating on Digital blocks within AMS projects (NXP/TI) rather than purely Digital projects (like AMD/Intel). It is essential that you have experience working on higher nodes such as 140nm, 180nm, 190nm, etc. Understanding Digital basics like DFF (D Flipflop) functionality is required, covering the fundamental aspects. Proficiency in Cadence tools is a must, along with knowledge of DFT insertion and hands-on experience with full chip tape out. Your ability to create and execute project plans leading up to the final tape out will be crucial for success in this role.,

You will be joining the global AMS team, which is responsible for the development of high-performance Mixed Signal blocks. The team oversees the physical implementation and integration of the blocks in the IC. Additionally, the team is involved in validation and collaborates closely with Architects and Application Engineers to derive Specs. As a member of the team, your responsibilities will include defining architecture and implementing transistor-level design of analog and mixed-signal blocks for Power efficient IoT ICs. You will also drive system-level specification and partitioning in collaboration with Systems and Application teams. Performing pre- and post-layout simulations and analysis across PVT corners using industry-standard EDA tools will be a crucial part of your role. Moreover, you will work closely with layout engineers to optimize performance, area, and noise/EMI sensitivity. Collaboration with cross-functional teams across design, verification, test, validation will be essential. You will also support silicon bring-up, characterization, and debug processes, as well as mentor junior designers. Producing high-quality review and spec documents, promoting IP reuse, documentation best practices, and patent/IP generation initiatives will also be part of your responsibilities. To qualify for this role, you are required to have a Masters or PhD in ECE or a related field, along with 5+ years of hands-on experience in analog/mixed-signal IC design, focusing on low power designs. Deep expertise in analog circuit design and system-level integration is necessary, as well as strong experience with Cadence tools and analog simulation methodologies. Demonstrated leadership in delivering complex designs from concept to production, excellent problem-solving, communication, and collaboration skills are also essential. Experience with 22nm/40nm is a plus, along with a proven track record of successful silicon tape-outs and production ramp. Knowledge of industry design standards and practices for reliability and safety, as well as an understanding of layout impact on analog performance and EMC/EMI mitigation, are required qualifications. Joining this team not only offers you the opportunity to work with highly skilled professionals who make a significant impact on the product but also provides benefits and perks such as Equity Rewards (RSUs), Employee Stock Purchase Plan (ESPP), insurance plans with Outpatient cover, National Pension Scheme (NPS), flexible work policy, and childcare support.,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.? Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world.? Job Description We are seeking a Principal Analog Design Engineer to lead the architecture, design, and development of Power Management ICs (PMICs). This is a high-impact technical leadership role, focused on designing complex, high-performance analog and mixed-signal circuits with emphasis on quality, reliability, and innovation. Key Responsibilities Define architecture and lead transistor-level design of analog and mixed-signal blocks for PMICs, including: LDOs, DC-DC converters (Buck/Boost), Voltage supervisors, Power sequencing, Load switches, Bandgap references, ADCs, Oscillators, and Bias circuits Drive system-level specification and partitioning in collaboration with Systems and Application teams Perform pre- and post-layout simulations and analysis across PVT corners using industry-standard EDA tools Work closely with layout engineers to optimize performance, area, and noise/EMI sensitivity Collaborate with cross-functional teams across design, verification, test, validation, and reliability Ensure designs meet functional safety, reliability, and regulatory compliance standards Support silicon bring-up, characterization, and debug Mentor junior designers and lead design reviews Promote IP reuse, documentation best practices, and patent/IP generation initiatives Qualifications Bachelors, Masters, or PhD in Electrical Engineering or related field 15+ years of hands-on experience in analog/mixed-signal IC design, with a focus on PMICs Deep expertise in analog circuit design, power management, and system-level integration Familiarity with ISO 26262, AEC-Q100, and other quality/reliability standards Strong experience with Cadence tools and analog simulation methodologies Demonstrated leadership in delivering complex designs from concept to production Excellent problem-solving, communication, and collaboration skills Experience with high-voltage BCD processes (e.g., 40V/60V) Proven track record of successful silicon tape-outs and production ramp Knowledge of industry design standards and practices for reliability and safety Understanding of layout impact on analog performance and EMC/EMI mitigation We recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer: Disability/Veteran Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis, as well as simulation debug with timing/SDF. It is expected that you have hands-on experience working on at least one SoC project from start to end. In addition to technical skills, you should possess qualities such as proactiveness, collaboration, and attention to detail. The ability to exercise independent judgment, debug issues, and identify root causes of simulation failures is crucial for this position. Strong interpersonal skills, effective communication (both oral and written), and self-motivation are also key attributes that will contribute to your success. At NXP in India, we value individuals who exhibit curiosity, a desire to understand the underlying mechanisms of their work, and a continuous drive for learning and improvement. If you are someone who thrives in a dynamic and challenging environment, where your contributions can make a significant impact, we encourage you to apply and join our team.,

Job description Job Description The Foundation IP Corporate Memory Organization is looking for an experienced Memory Layout Designer to join its team. Develop custom layout design for memory compilers (e.g., bit cells, SRAMs, Register Files). Perform detailed physical array planning, area optimization, critical wire analysis, and custom leaf cell layout. Conduct complete layout verification including design rule compliance, electromigration, voltage drop (IR), selfheat, and other reliability checks. May use custom autorouters and custom placers to efficiently construct layout. Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests. Develop and drive new and innovative layout methods to improve productivity and quality. Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design. Qualifications Hands-on experience with layouts of critical memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc., in compiler context. Solid experience with custom Memory (SRAM, RF, ROM) layout physical design Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electro migration, voltage drop (IR), ESD, and other reliability checks on the layouts. Develops custom layout design memory compilers (e.g., bit cells, SRAMs, Register Files), performs area impact assessment with updated PDKs. Performs detailed physical array planning, power planning, area optimization, critical wire analysis, custom leaf cell layout. Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Knowledge of and experience with advanced FinFET processes in 5nm. Solid experience using Cadence Virtuoso for custom layout physical design Scripting knowledge/ SKILL coding is a plus. Years of Experience: Bachelors with 3 to 6 yrs of experience. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

You are an experienced AMS Verification Engineer with over 8 years of expertise in AMS IC verification, possessing hands-on experience in VerilogAMS, SystemVerilog, and UVM. Your strong skills lie in VerilogAMS and Real Number Modeling, and you have a solid understanding of Cadence tools, VManager, and Tcl/Perl. Any knowledge or experience in Analog/RF would be considered a valuable advantage. The location for this position is in Bengaluru. If you believe you are a suitable candidate for this role, we encourage you to reach out by either sending a direct message or sharing your CV to aayushi.sharma@saracasolutions.com. Join us in shaping the future of semiconductors!,

As a Design Engineer - II at TekWissen Group in Noida, you will be responsible for hardware board design in a customer-centric information technology environment. You should possess a Bachelor's degree in electronics, product & industrial design, or a related field, with a Master's degree considered a plus. With a minimum of 8+ years of experience in hardware board design or a similar manufacturing environment, you are expected to have a solid understanding of the manufacturing process, quality requirements, and DFM process. Your role will require expertise in high-speed digital signal design and testing, as well as a thorough understanding of electronics components. Proficiency in Cadence tools, including Allegro and OrCAD, and experience with Hierarchical design are essential. You should have strong technical and analytical skills to troubleshoot and debug electronic systems effectively. Experience with NXP processors, DDR4, Power designs, and RF designs is necessary for this position. Excellent interpersonal and communication skills, teamwork adaptability, and proficiency in oral and written English are highly valued. As an equal opportunity employer, TekWissen Group supports workforce diversity to foster an inclusive work environment.,

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPS and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ? 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows Basic Qualifications Bachelor&aposs in Electronics /Electrical Engineering (Master&aposs preferred). 5+ years of digital design experience, with 3+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise Hands-on experience with processor IP (ARM/ARC) Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Silicon bring-up and post-silicon debug experience. Familiarity with Synopsys/Cadence tools and UVM-based design verification. Preferred Experience Hands-on experience with complex DMA engines and FW interaction Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience with block-level and full-chip design at advanced nodes (? 16nm). Understanding of PAD design, DFT, and floor planning. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Show more Show less

As part of the custom product business at our company, you will be contributing to the development of industry-leading custom IC system solutions across various product categories such as display and touch power products, camera PMICs, charger power products, power switches/muxes, Laser drivers, and high-speed communication interfaces. By integrating signal chain and power components, your work will play a key role in enabling our customers to enhance their next-gen products in the personal electronics domain. Joining our team presents a unique opportunity to be part of a world-class custom semiconductor team. Your responsibilities in this role will include verifying complex analog designs/systems and providing support for the validation of designs on silicon. You will be responsible for releasing meticulously analyzed and simulated IC designs in a timely manner, ensuring they deliver optimal performance, cost-effectiveness, high quality, and meet our customers" end system requirements. Additionally, you will define, specify, model, plan, and implement the AMS verification strategy for mixed-signal ICs, including creating detailed verification plans and test cases, evaluating system-level use-cases, and contributing to post-layout parasitic extraction and simulation activities. To excel in this role, you are expected to have a strong background in defining and developing verification infrastructure for mixed-signal semiconductor products, along with a good understanding of analog circuits and expertise in tools such as Cadence Virtuoso, Cadence Spectre/TISpice, and Verilog-AMS/SystemVerilog. Proficiency in scripting languages like Python and Perl, as well as the ability to collaborate effectively with cross-functional teams, are essential skills for success in this position. Additionally, problem-solving abilities, strong communication skills, and the capacity to manage tasks independently with minimal supervision are key attributes we are looking for. With a minimum of 7 years of experience in mixed-signal verification and proficiency in tools like Virtuoso, Verilog, Verilog AMS, and Cadence tools such as xrun/ncsim/Vmanager, you will be well-equipped to meet the demands of this role. This position offers you the opportunity to work in a global organization, lead design and verification projects, and contribute to continuous improvements in design verification strategies, tools, methods, and flows. If you are passionate about shaping the future of electronics and seek a collaborative, innovative work environment, we invite you to apply for this exciting opportunity at our company. At Texas Instruments, we are committed to creating a better world through affordable electronics, and we value diversity and inclusivity in our workforce. Join us in engineering your future and being a part of our mission to drive innovation in the semiconductor industry. Please note that Texas Instruments is an equal opportunity employer and fosters a diverse and inclusive work environment. If you meet the qualifications outlined above and are interested in this position, we encourage you to apply.,

Experience: 5 + Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills Skills Required Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Location Hyderabad, India Desirable Skills Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Designation Associate

Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills

Roles and Responsibilities Develop RTL code using Verilog/VHDL Work with Mentor DfT tools and Cadence tools for design and verification Perform scan insertion, JTAG, ATPG DRC, and coverage analysis Debug simulations using timing and SDF Contribute to LBIST and Mixed Signal Radar IC-related projects (preferred) Investigate simulation failures and perform root cause analysis Collaborate with cross-functional teams; work independently and proactively Communicate effectively with both written and verbal communication

Job Details: You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for power delivery network design, IR Drop analysis and convergence of complex core design. Your Responsibilities Will Include But Not Limited To Responsible for power delivery network design including package/bump to device level delivery for over 5GHz Freq and low-power digital designs. Deep understanding of RV and IR Drop concepts. Load line definition Closely work with SD, Integration and Floor plan teams Qualifications: * You must possess a master's degree in electrical or Electronics Engineering with at least 6 or more years of experience in related field or a bachelor's degree with at least 8 years of experience. * With a deep Technical Expertise On - power delivery network IR and RV analysis, MIM spread with Tools: Redhawk, RHSC Additional preferred Skills being. * Technical Expertise in Static Timing Analysis is preferred. * Preferred Additional Skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Shift: Shift 1 (India)

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.