11 Cadence Tools Jobs

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis, as well as simulation debug with timing/SDF. It is expected that you have hands-on experience working on at least one SoC project from start to end. In addition to technical skills, you should possess qualities such as proactiveness, collaboration, and attention to detail. The ability to exercise independent judgment, debug issues, and identify root causes of simulation failures is crucial for this position. Strong interpersonal skills, effective communication (both oral and written), and self-motivation are also key attributes that will contribute to your success. At NXP in India, we value individuals who exhibit curiosity, a desire to understand the underlying mechanisms of their work, and a continuous drive for learning and improvement. If you are someone who thrives in a dynamic and challenging environment, where your contributions can make a significant impact, we encourage you to apply and join our team.,

Job description Job Description The Foundation IP Corporate Memory Organization is looking for an experienced Memory Layout Designer to join its team. Develop custom layout design for memory compilers (e.g., bit cells, SRAMs, Register Files). Perform detailed physical array planning, area optimization, critical wire analysis, and custom leaf cell layout. Conduct complete layout verification including design rule compliance, electromigration, voltage drop (IR), selfheat, and other reliability checks. May use custom autorouters and custom placers to efficiently construct layout. Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests. Develop and drive new and innovative layout methods to improve productivity and quality. Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design. Qualifications Hands-on experience with layouts of critical memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc., in compiler context. Solid experience with custom Memory (SRAM, RF, ROM) layout physical design Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electro migration, voltage drop (IR), ESD, and other reliability checks on the layouts. Develops custom layout design memory compilers (e.g., bit cells, SRAMs, Register Files), performs area impact assessment with updated PDKs. Performs detailed physical array planning, power planning, area optimization, critical wire analysis, custom leaf cell layout. Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Knowledge of and experience with advanced FinFET processes in 5nm. Solid experience using Cadence Virtuoso for custom layout physical design Scripting knowledge/ SKILL coding is a plus. Years of Experience: Bachelors with 3 to 6 yrs of experience. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

You are an experienced AMS Verification Engineer with over 8 years of expertise in AMS IC verification, possessing hands-on experience in VerilogAMS, SystemVerilog, and UVM. Your strong skills lie in VerilogAMS and Real Number Modeling, and you have a solid understanding of Cadence tools, VManager, and Tcl/Perl. Any knowledge or experience in Analog/RF would be considered a valuable advantage. The location for this position is in Bengaluru. If you believe you are a suitable candidate for this role, we encourage you to reach out by either sending a direct message or sharing your CV to aayushi.sharma@saracasolutions.com. Join us in shaping the future of semiconductors!,

As a Design Engineer - II at TekWissen Group in Noida, you will be responsible for hardware board design in a customer-centric information technology environment. You should possess a Bachelor's degree in electronics, product & industrial design, or a related field, with a Master's degree considered a plus. With a minimum of 8+ years of experience in hardware board design or a similar manufacturing environment, you are expected to have a solid understanding of the manufacturing process, quality requirements, and DFM process. Your role will require expertise in high-speed digital signal design and testing, as well as a thorough understanding of electronics components. Proficiency in Cadence tools, including Allegro and OrCAD, and experience with Hierarchical design are essential. You should have strong technical and analytical skills to troubleshoot and debug electronic systems effectively. Experience with NXP processors, DDR4, Power designs, and RF designs is necessary for this position. Excellent interpersonal and communication skills, teamwork adaptability, and proficiency in oral and written English are highly valued. As an equal opportunity employer, TekWissen Group supports workforce diversity to foster an inclusive work environment.,

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPS and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ? 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows Basic Qualifications Bachelor&aposs in Electronics /Electrical Engineering (Master&aposs preferred). 5+ years of digital design experience, with 3+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise Hands-on experience with processor IP (ARM/ARC) Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Silicon bring-up and post-silicon debug experience. Familiarity with Synopsys/Cadence tools and UVM-based design verification. Preferred Experience Hands-on experience with complex DMA engines and FW interaction Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience with block-level and full-chip design at advanced nodes (? 16nm). Understanding of PAD design, DFT, and floor planning. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Show more Show less

As part of the custom product business at our company, you will be contributing to the development of industry-leading custom IC system solutions across various product categories such as display and touch power products, camera PMICs, charger power products, power switches/muxes, Laser drivers, and high-speed communication interfaces. By integrating signal chain and power components, your work will play a key role in enabling our customers to enhance their next-gen products in the personal electronics domain. Joining our team presents a unique opportunity to be part of a world-class custom semiconductor team. Your responsibilities in this role will include verifying complex analog designs/systems and providing support for the validation of designs on silicon. You will be responsible for releasing meticulously analyzed and simulated IC designs in a timely manner, ensuring they deliver optimal performance, cost-effectiveness, high quality, and meet our customers" end system requirements. Additionally, you will define, specify, model, plan, and implement the AMS verification strategy for mixed-signal ICs, including creating detailed verification plans and test cases, evaluating system-level use-cases, and contributing to post-layout parasitic extraction and simulation activities. To excel in this role, you are expected to have a strong background in defining and developing verification infrastructure for mixed-signal semiconductor products, along with a good understanding of analog circuits and expertise in tools such as Cadence Virtuoso, Cadence Spectre/TISpice, and Verilog-AMS/SystemVerilog. Proficiency in scripting languages like Python and Perl, as well as the ability to collaborate effectively with cross-functional teams, are essential skills for success in this position. Additionally, problem-solving abilities, strong communication skills, and the capacity to manage tasks independently with minimal supervision are key attributes we are looking for. With a minimum of 7 years of experience in mixed-signal verification and proficiency in tools like Virtuoso, Verilog, Verilog AMS, and Cadence tools such as xrun/ncsim/Vmanager, you will be well-equipped to meet the demands of this role. This position offers you the opportunity to work in a global organization, lead design and verification projects, and contribute to continuous improvements in design verification strategies, tools, methods, and flows. If you are passionate about shaping the future of electronics and seek a collaborative, innovative work environment, we invite you to apply for this exciting opportunity at our company. At Texas Instruments, we are committed to creating a better world through affordable electronics, and we value diversity and inclusivity in our workforce. Join us in engineering your future and being a part of our mission to drive innovation in the semiconductor industry. Please note that Texas Instruments is an equal opportunity employer and fosters a diverse and inclusive work environment. If you meet the qualifications outlined above and are interested in this position, we encourage you to apply.,

Experience: 5 + Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills Skills Required Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Location Hyderabad, India Desirable Skills Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Designation Associate

Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills

Roles and Responsibilities Develop RTL code using Verilog/VHDL Work with Mentor DfT tools and Cadence tools for design and verification Perform scan insertion, JTAG, ATPG DRC, and coverage analysis Debug simulations using timing and SDF Contribute to LBIST and Mixed Signal Radar IC-related projects (preferred) Investigate simulation failures and perform root cause analysis Collaborate with cross-functional teams; work independently and proactively Communicate effectively with both written and verbal communication

Job Details: You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for power delivery network design, IR Drop analysis and convergence of complex core design. Your Responsibilities Will Include But Not Limited To Responsible for power delivery network design including package/bump to device level delivery for over 5GHz Freq and low-power digital designs. Deep understanding of RV and IR Drop concepts. Load line definition Closely work with SD, Integration and Floor plan teams Qualifications: * You must possess a master's degree in electrical or Electronics Engineering with at least 6 or more years of experience in related field or a bachelor's degree with at least 8 years of experience. * With a deep Technical Expertise On - power delivery network IR and RV analysis, MIM spread with Tools: Redhawk, RHSC Additional preferred Skills being. * Technical Expertise in Static Timing Analysis is preferred. * Preferred Additional Skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Shift: Shift 1 (India)

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.