45 Cadence Tools Jobs

Role Overview: You are required to lead the end-to-end VLSI components and hardware systems, providing customer support and governance of VLSI components and hardware systems, and managing the team effectively. Key Responsibilities: - Design, analyze, develop, modify, and evaluate VLSI components and hardware systems - Determine architecture and logic design verification through software for component and system simulation - Conduct system evaluations, make appropriate recommendations, and review data and project documentation - Identify and recommend system improvements for better technical performance - Inspect VLSI components and hardware systems for compliance with regulations and safety...

As an experienced Layout Memory Engineer, your role will involve hands-on experience with important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. You should have a strong background in working with 16nm/14nm/10nm/7nm/Finfet process technologies and top-level memory integration, along with expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. Your responsibilities will also include addressing IR/EM related issues in memory layouts and utilizing Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A solid understanding of ultra-de...

Job Title: Digital Backend Design Engineer Location: Bangalore Experience: 610 Years Job Description We are seeking an experienced Digital Backend Design Engineer with strong hands-on expertise in digital backend design flows, physical verification, low-power methodologies, and scripting. The candidate will work with leading EDA tools from Cadence and Synopsys , contributing to complex digital design projects. Key Responsibilities Perform digital backend design using Cadence and Synopsys tools. Conduct physical verification using Mentor Calibre or Cadence PVS tools. Apply low-power design techniques and implement UPF methodology. Develop and maintain scripts in TCL, Shell, Perl, or Python to...

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About The Job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. JD for CIC Frontend req AE3 Your role will be to meet customers/prospects and identify & qualify the opportunities, work out agreeable and achievable evaluation criteria, run through the evaluation and convert the opportunities into business leading to deployment of an efficient circuit simulation and mixed signal methodology using Cadence tools. It requires a very good understanding of customer flow & challenges and a good analytical ability to resolve issues impacting production schedule. Handson knowledge / experience on analog and mixed-signal circuit Design / Debug / modeling an...

Role Overview: As a Layout Design Engineer, your main role will involve hands-on experience with layouts of important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in a compiler context. You should have worked on 16nm / 14nm / 10nm / 7nm / Finfet process technologies. Additionally, you should have hands-on experience with top-level memory integration and expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. A good handle on IR/EM related issues in memory layouts is also essential. Key Responsibilities: - Work on layouts of memory building blocks in a compiler context - Ensure top-level memory integr...

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities: ? Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. ? Perform Static Timing Analysis (STA) and ensure timing closure across all design corners. ? Execute power integrity and physical verification checks (LVS, DRC). ? Co...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with programming languages such as Perl, Python, or TCL. Experience in managing block physical implementation and Quality of Results (QoR). Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with computer architecture. Experience with constraints, synthesis or Clock Tree Synthesis (CTS)...

Experience: 10+ years Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Leading junior teams, Mentoring/Trainin...

As part of the Embedded Processors group of TI, you will be working with the Processors and Application Specific Microcontroller (ASM) Business Units. Your role will involve developing cutting-edge system-on-chips (SoCs) for microcontrollers and processors, including 5nm technologies, for industrial and automotive applications. The team is known for creating differentiated IPs with patented technologies that enhance ADAS, Zonal, Domain controller, and Real-Time Control application performance. Your responsibilities will include designing high-performance CPU cores, math co-processors, interconnects, networking and multimedia controllers, safety and security infrastructure, and control and co...

Role We are looking for a talented a R&D Hardware Engineer to design, develop, and validate electronic hardware for intelligent devices used in commercial building HVAC systems. This role involves working closely with cross-functional teams to deliver reliable, energy-efficient, and standards-compliant solutions for modern building automation. We are looking for a positive, confident, and self-motivated individual who thrives in a fast-paced, team-based environment and is passionate about developing next-generation technologies that connect and empower our products and customers. Responsibilities: Design analog and digital circuits for intelligent devices ranging from environmental sensor, p...

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation 2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology) 3. Implementation of a project with the full Cadence tools 4. Have worked on complex Hard macros with SerDes and/or critical in timing and area 5. Having experience in Flip-Chip SoC bump Ios) 6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: ...

Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are seeking a highly skilled and motivated STA (Static Timing Analysis) Engineer to join our team specializing in timing analysis for cutting-edge and complex SoC projects. This role offers a unique opportunity to work on high-level designs and collaborate with multidisciplinary teams in a dynamic and challenging environment. Your Responsibilities May Include But Not Be Limited To STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Tim...

Job Description: Analog layout designer providing onsite support for advanced nodes, working with global layout and design team. Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout. Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc. Should have worked on and top-level integration Should have a good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, preference will be given to FinFet experience candidates. Should have a g...

Role Overview: Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to mak...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. We are seeking a Principal Digital Design Engineer with deep expertise in high-performance controller an...

We are looking for highly experienced Senior ASIC Engineers to lead and contribute to complex ASIC projects. This role requires expertise in advanced physical design, verification, and tapeout processes. The ideal candidate will have a proven track record of delivering high-quality ASIC designs in advanced technology nodes. Responsibilities: Lead and execute complex physical design implementations, including block-level low power aware floorplanning, placement, CTS, routing, RC extraction, STA, IR/EM analysis, and DRC/LVS/ERC. Manage hierarchical physical verification and signoff closures. Develop and implement advanced UVM verification environments for IP and full-chip verification. Verify ...

As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and ...