Memory Layout engineer

3 - 7 years

0 Lacs

Posted:1 day ago| Platform: Shine logo

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Work Mode

On-site

Job Type

Full Time

Job Description

As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and Cadence/Mentor tools for physical verification checks. - Strong knowledge of ultra-deep sub-micron layout design challenges and DFM guidelines. - Experience or a strong interest in memory Macros or Memory Compiler. - Demonstrated ability to be an excellent team player and work effectively with external customers.,

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Quest Global

Engineering Services

Beachwood

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