3.0 - 5.0 years

0 Lacs

hyderabad, telangana, india

On-site

Job Requirements Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory Good hold on IR/EM related issues in memory layouts. Experience Required: 3+ yrs Work Experience Skills Required: Must have worked on cadence tools for layout design and Cadence/Mentor tools for physical verification checks. Strong knowledge of ultra-deep sub-micron layout design related cha...

Posted 1 month ago

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Associate III - VLSI ML UST Global

3.0 - 8.0 years

0 Lacs

karnataka

On-site

Role Overview: You should have the ability to execute any small to mid-size customer project in VLSI Frontend, Backend, or Analog design with minimal supervision. Your role involves working as an individual contributor on tasks such as RTL Design/Module and providing support to junior engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your successful and on-time completion of assigned tasks will be crucial, with quality delivery approved by the project lead/manager. Key Responsibilities: - Work as an individual contributor on tasks such as RTL Design/Module and support junior engineers in various areas - Independe...

Posted 2 months ago

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Memory Layout engineer Quest Global

3.0 - 7.0 years

0 Lacs

hyderabad, telangana

On-site

As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and ...

Posted 3 months ago

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Associate III - VLSI ML UST Global

3.0 - 8.0 years

0 Lacs

karnataka

On-site

The role requires 3 to 8 years of experience in SRAM Memories layout design. You should be well-versed in various levels of memory layouts including custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, and decoders. Proficiency in floor planning, power planning, block area estimation of memory designs or compliers is essential. You must have expertise in leaf cell layout development and physical verification. Additionally, a good understanding of schematics, interface with circuit designer and CAD, and process development team is required. Strong knowledge of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, ma...

Posted 5 months ago

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