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3.0 - 5.0 years
0 Lacs
hyderabad, telangana, india
On-site
Job Requirements Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory Good hold on IR/EM related issues in memory layouts. Experience Required: 3+ yrs Work Experience Skills Required: Must have worked on cadence tools for layout design and Cadence/Mentor tools for physical verification checks. Strong knowledge of ultra-deep sub-micron layout design related cha...
Posted 3 days ago
6.0 - 10.0 years
0 Lacs
karnataka
On-site
Role Overview: As a Memory Layout Engineer at GlobalFoundries, you will be a vital part of the team responsible for developing layout for SRAM/ROM memory circuits, supporting customers in designing high-quality products using advanced process nodes. Your main responsibilities will include: Key Responsibilities: - Developing product grade SRAM memory IPs - Conducting layout design of SRAM Memory IPs - Performing layout checks such as LVS, DRC, DFM, EMIR - Reviewing layouts and providing assistance to other Layout teams - Preparing design kits from the layout side, and verifying and validating them - Providing support for layout automation and script support - Taking initiatives for productivi...
Posted 3 weeks ago
2.0 - 6.0 years
2 - 6 Lacs
bengaluru, karnataka, india
On-site
The development of product grade SRAM memory IP s covering the following phases: Layout Design of SRAM Memory IPs Layout checks like LVS,DRC,DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team-player taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of the silicon bring up and characterization Required Qualifications: Bachelor s degree with 8+ years or master s degree with 6+ years experience in semiconductors / Microelectronics / VLSI engineeri...
Posted 1 month ago
3.0 - 7.0 years
0 Lacs
hyderabad, telangana
On-site
As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and ...
Posted 1 month ago
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