6 Dfm Guidelines Jobs

Job Requirements Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory Good hold on IR/EM related issues in memory layouts. Experience Required: 3+ yrs Work Experience Skills Required: Must have worked on cadence tools for layout design and Cadence/Mentor tools for physical verification checks. Strong knowledge of ultra-deep sub-micron layout design related cha...

As an experienced Layout Memory Engineer, your role will involve hands-on experience with important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. You should have a strong background in working with 16nm/14nm/10nm/7nm/Finfet process technologies and top-level memory integration, along with expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. Your responsibilities will also include addressing IR/EM related issues in memory layouts and utilizing Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A solid understanding of ultra-de...

Role Overview: As a Layout Design Engineer, your main role will involve hands-on experience with layouts of important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in a compiler context. You should have worked on 16nm / 14nm / 10nm / 7nm / Finfet process technologies. Additionally, you should have hands-on experience with top-level memory integration and expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. A good handle on IR/EM related issues in memory layouts is also essential. Key Responsibilities: - Work on layouts of memory building blocks in a compiler context - Ensure top-level memory integr...

As a Physical Verification Engineer, you will be responsible for performing layout verification of integrated circuits (ICs) using industry-standard tools. Your role will include checking for DRC, LVS, ERC, and other checks to ensure the design is manufacturable and compliant with foundry rules. Key Responsibilities: - Perform layout verification of ICs using industry-standard tools - Check for DRC, LVS, ERC, and other verification checks - Ensure the design is manufacturable and compliant with foundry rules Qualifications Required: - 4-7 years of experience in physical verification of IC layout - Proficiency in industry-standard physical verification tools - Strong understanding of DRC, LVS...

As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and ...

The position is based in Andheri, Mumbai and requires 2-3 years of experience in complex PCB design and layout for industrial applications. As a PCB Design Engineer, you will be responsible for designing and executing multi-layer PCB layouts from concept to production. This includes creating and optimizing high-density, high-speed PCB designs, generating Gerber files for manufacturing, and performing impedance calculations and signal integrity analysis. You will need to implement PCB design rules and design for manufacturing (DFM) guidelines, conduct thermal analysis, and optimize component placement. Additionally, you will lead design reviews, mentor junior PCB designers, and coordinate wit...