8 Decoders Jobs

Role & responsibilities Design and optimization of SRAMs, ROMs, CAMs, sense amps, bitcells, decoders, and more. Development of analog/mixed-signal IPs op-amps, comparators, LDOs, bandgaps, DAC/ADC circuits. Creation of custom digital standard cells optimized for PPA. Schematic design, simulation (across PVT), layout collaboration, and sign-off (DRC/LVS/ERC). Support automation flows using TCL, Perl, Python, Shell. Work cross-functionally with architecture, layout, and technology teams . Preferred candidate profile 5+ years in analog/mixed-signal and custom circuit design. Proven tape-out experience at advanced nodes. Strong in simulation, layout-aware design, and verification best practices....

As an experienced Layout Memory Engineer, your role will involve hands-on experience with important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. You should have a strong background in working with 16nm/14nm/10nm/7nm/Finfet process technologies and top-level memory integration, along with expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. Your responsibilities will also include addressing IR/EM related issues in memory layouts and utilizing Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A solid understanding of ultra-de...

Role Overview: As a Layout Design Engineer, your main role will involve hands-on experience with layouts of important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in a compiler context. You should have worked on 16nm / 14nm / 10nm / 7nm / Finfet process technologies. Additionally, you should have hands-on experience with top-level memory integration and expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. A good handle on IR/EM related issues in memory layouts is also essential. Key Responsibilities: - Work on layouts of memory building blocks in a compiler context - Ensure top-level memory integr...

As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and ...

Xeedo Technologies is looking for a Senior Analog Layout Engineer with 5 to 8 years of experience to join the team in Phoenix Aquila, Hyderabad, India. In this role, you will be working on-site for Micron Technology, a global semiconductor leader. Your responsibilities will include owning analog/custom layout blocks, performing physical verification, and collaborating with global design teams to ensure successful project execution and tape-outs. You will be responsible for designing and developing analog and custom digital layout blocks in advanced CMOS technologies. This will involve using Mentor Graphics Calibre for full physical verification, including DRC, LVS, and Antenna checks. Your g...

Company Description SILCOSYS Solutions collaborates with clients to develop next-generation flagship products, including mobile devices, routers, consumer goods, storage solutions, microprocessors, and graphics processors. We are known for pioneering cutting-edge technologies that are both pivotal and rare in the industry. With expertise in crafting intricate SoCs, SILCOSYS Solutions also boasts one of the industry&aposs most robust analog/mixed signal and software design teams. Position: Senior Memory Layout Engineer Experience: 6 - 15 Years Location: Bangalore Notice Period: 0 - 15 Days Role Description Looking for experts in memory compilers with solid hands-on experience in SRAM, ROM, TC...

Join our AI team as a Generative AI Engineer! Work on LLMs, prompt engineering, and model fine-tuning. Ideal for freshers or those with up to 2 years of experience in Python, ML, and deep learning. Passion for AI is a must!

5 days Working & 24*7 Support Pick and Drop Cab facility Open role- 1- Specialist- Compression 2- Lead- Compression KEY RESPONSIBILITIES Operation & Maintenance- Technical knowledge of disciplines like video compression (MPEG-2, MPEG-4), digital video broadcast (DVB), video servers, Streaming Technologies, IP networking, Set-top boxes, EPG, and Web-based client/server applications. Regular maintenance of equipments (Encoders , Receivers , NMS, etc.). Knowledge of CAS system - Simulcryption and good understanding of Encryption, decryption, Access criteria, ECMs and EMMs. Provide Technical Support to various departments for Audio/Video, MPEG and DVB domain & S/w Tests such as OTA, Manual Tunin...