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3.0 - 5.0 years
0 Lacs
hyderabad, telangana, india
On-site
Job Requirements Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory Good hold on IR/EM related issues in memory layouts. Experience Required: 3+ yrs Work Experience Skills Required: Must have worked on cadence tools for layout design and Cadence/Mentor tools for physical verification checks. Strong knowledge of ultra-deep sub-micron layout design related cha...
Posted 3 days ago
3.0 - 7.0 years
0 Lacs
hyderabad, telangana
On-site
As a Memory Layout Engineer, you will be responsible for the following: - Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, and decoders. - Should have worked on at least 7nm Finfet process technologies. Knowledge of 6nm, 5nm, 4nm, 3nm will be an added advantage. - Proficient in top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the Memory. - Good understanding of IR/EM related issues in memory layouts. Qualifications required for this role include: - Minimum of 3 years of experience in Memory Layout Engineering. - Proficiency in Cadence tools for layout design and ...
Posted 1 month ago
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