ASIC/SOC Front End DV (Design Verification) Engineer

Role: ASIC/SOC Front End DV (Design Verification) Engineer

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  A major part of your responsibility will be to take an independent verification role in developing TB architecture definition and TB infrastructure/test coding development for PCIe/Networking/IP Sub-Systems.

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  Understanding product specifications and deriving the TB architectures.

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  Developing verification plan, test plan, coverage plan, assertions, etc.

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  Developing block-level and multi block-level verification environments & reusable verification components based on SV/UVM methodology.

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  Coverage metrics to ensure conformity, running regressions, debug test failures, and regression management.

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  Knowledge and working experience with any of the complex protocols like PCIe/Ethernet/DMAs/Cryptography/Others – an advantage.

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  Experience in scripting languages like Perl or Python.

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  Knowledge in AMBA AXI, APB, etc. – an advantage.

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  Ability to work collaboratively with other team members and have good ownership and accountability.

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  Assisting validation teams with on board-level test issues, educating design teams on verification methodology.

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  Contributing to process improvement in verification methodologies that impact productivity.

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  Strong oral and written communication skills, problem-solving and analytical skills.

Job Requirements:

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  Working experience with latest SOC tools including Questa, Cadence Conformal, VCS simulation.

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  B.E/M.E/M.Tech or B.S/M.S in EE/CE