ASIC/SOC Front End DV (Design Verification) Engineer

Role Overview: As an ASIC/SOC Front End DV (Design Verification) Engineer, you will play a crucial role in the development of TB architecture definition and TB infrastructure/test coding for PCIe/Networking/IP Sub-Systems. Your responsibilities will include understanding product specifications, developing verification plans, test plans, coverage plans, assertions, and more. You will be expected to collaborate with team members, work on verification methodologies, and contribute to process improvements. Key Responsibilities: - Develop TB architectures and verification environments based on SV/UVM methodology - Create verification plans, test plans, coverage metrics, and assertions - Implement block-level and multi block-level verification environments - Run regressions, debug test failures, and manage regression activities - Work with protocols like PCIe/Ethernet/DMAs/Cryptography - Utilize scripting languages such as Perl or Python - Familiarity with AMBA AXI, APB is an advantage - Collaborate with validation teams and educate design teams on verification methodology - Contribute to process improvement in verification methodologies - Demonstrate strong communication, problem-solving, and analytical skills Qualification Required: - 3-10+ years of relevant experience - Working experience with tools like Questa, Cadence Conformal, VCS simulation - Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (Note: No additional details of the company were provided in the job description),