Digital verification engineer STMicroelectronics

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a semiconductor company, ST believes in the power of technology to drive innovation and make a positive impact on people, business, and society. You will be part of a global business of diverse creators and makers from over 115 nationalities, dedicated to pushing boundaries and driving innovation around the world. Join ST to unlock your potential and be a part of shaping the future with cutting-edge technology. **Role Overview:** As part of the verification team, your main responsibility will be to drive towards zero-defect by developing verification test benches, verification components, and test cases for simulation. You will also be involved in debugging failures and creating simulatio...

Posted 1 week ago

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SOC DV Source-Right

3.0 - 7.0 years

0 Lacs

bangalore, karnataka

On-site

As a SOC DV (SI58FT RM 3600) you will be responsible for: - Having a good understanding of AMBA AXI, AHB, APB protocols. - Being well versed with SystemVerilog. - Having basic knowledge of C language. - Possessing good debug skills. - Having basic knowledge of UVM. Qualifications required: - Strong understanding of AMBA AXI, AHB, APB protocols. - Proficiency in SystemVerilog. - Basic knowledge of C language. - Strong debug skills. - Familiarity with UVM.,

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ASIC/SOC Front End DV (Design Verification) Engineer Proxelera

3.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: As an ASIC/SOC Front End DV (Design Verification) Engineer, you will play a crucial role in the development of TB architecture definition and TB infrastructure/test coding for PCIe/Networking/IP Sub-Systems. Your responsibilities will include understanding product specifications, developing verification plans, test plans, coverage plans, assertions, and more. You will be expected to collaborate with team members, work on verification methodologies, and contribute to process improvements. Key Responsibilities: - Develop TB architectures and verification environments based on SV/UVM methodology - Create verification plans, test plans, coverage metrics, and assertions - Implement...

Posted 2 weeks ago

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