ASIC RTL Engineer / Digital Design

Role : ASIC RTL Engineer / Digital DesignLocation: Bangalore, Hyderabad, Pune

Mandatory Skill

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro ArchitecturePCIe/DDR/Ethernet - Any OneI2C,UART/SPI - Any OneSpyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any OneScripting languages like Make flow, Perl ,shell, python - Any One

Good To Have

processor architecture / ARM debug architecturedebug issues for multiple subsystemscreate/review design documents for multiple subsystemsAble to support physical design, verification, DFT and SW teams on design queries and reviews

Details JD

Expertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge of synthesis and low power is a plusGood understanding of AMBA bus protocols (AXI, AHB, ATB, APB)Good understanding of timing conceptsKnowledge of one or more of the interface protocols

• PCIe
• DDR
• Ethernet
• I2C, UART, SPI
  

Expertise in setting up and using tools like

• Spyglass Lint/CDC
• Synopsys DC
• Verdi/Xcellium
  

Understanding of scripting languages like Make flow, Perl ,shell, python etc
Understanding of processor architecture and/or ARM debug architecture is a plusAble to help and debug issues for multiple subsystemsAble to create/review design documents for multiple subsystemsAble to support physical design, verification, DFT and SW teams on design queries and reviewsThis job is provided by Shine.com