Asic RTL Design Lead Engineer

Greetings from Wafer Space! Exciting Opportunity for Senior RTL Design Lead Engineers Automotive SoC Domain Job Title: Senior RTL Design Engineer No. of Positions: 4 Notice Period: Immediate to 30 Days Only Referrals: Please refer only suitable and relevant profiles About the Role: We are looking for experienced RTL Design Engineers to join our team developing next-generation solutions for automotive camera and display systems. This is a key position requiring strong technical expertise in microarchitecture and RTL coding, with an emphasis on high-performance, low-power ASIC designs. Key Responsibilities: Define microarchitecture and implement RTL to meet performance, power, and area (PPA) goals. Collaborate with software teams to define hardware/software interfaces, configuration requirements, and verification collaterals. Partner with verification teams on assertion development, test plans, debugging, and coverage closure. Ensure adherence to industry-standard ASIC design methodologies. Drive design quality and functional safety for automotive-grade solutions. Required Skills & Qualifications: Bachelors/Masters/Ph.D. in Electrical/Electronics Engineering. 5–10 years of hands-on experience in RTL design and microarchitecture development. Strong proficiency in Verilog and SystemVerilog. Proven experience in designing IP blocks for video/audio pipelines. Sound understanding of MIPI CSI and DSI protocols. Experience with high-speed, pipelined, and low-power designs. Familiarity with EDA tools and design methodologies (e.g., Synopsys, Cadence). Experience working on designs complying with automotive functional safety (ISO 26262) is a plus. Excellent problem-solving, communication, and team collaboration skills. Note: Only candidates with a notice period of 30 days or less will be considered. Please share or refer profiles that are strictly relevant to the requirements.