776 Asic Jobs - Page 3

About Marvell . Your Team, Your Impact In this position you ll be a member of the Data Centre Custom Compute Group - DCE CCS BU in Marvell. You ll be part of the Signal integrity Team designing high performance hardware for the industry leading DCE-CCS-BU SoC products targeted for Datacenter, Storage and AI applications. Marvell Data Centre Custom Compute Group -DCE CCS BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Engage with Hardware Engineering, Package Design and SoC Design Teams to define the SI/PI requirements and dependencies with support. Perform pre-layout simulations and generate layout guidelines and checklists. Review schematics for the hardware and analyse the feasibility of hardware. Review design and guide PCB layout team for placement and layout for first-time-right design. Perform SI/PI simulation for the hardware and deliver error free reports. Measure fabricated PCBs and perform correlation between simulation and measured results. What Were Looking For Bachelor s degree in Electrical Engineering and 8+ years of related professional experience or Master s/PhD in Electrical Engineering with 6+ years of experience. Strong fundamentals in EM, transmission lines and microwave theory Experience in using 2-D and 3-D EM simulation tools such as Ansys HFSS, SI-Wave, Cadence Clarity, PowerSI. Experience on any of the schematic and layout tools - Cadence Allegro, Mentor Expedition, Orcad Ability to manage hardware development involving various cross functional teams like HW Design, PCB layout, Hardware assembly, IC packaging teams, Analog and Digital designers, marketing and PCB Fab vendors. Ability to automate the SI, PI and Packaging activities using scripting tools like Python, TCL. Power plane design, modeling and analysis using tools like PowerSI, Power DC, SIwave Working knowledge of circuit analysis tools: ADS, HSpice Frequency domain and time domain knowledge of high speed signaling Familiarity with PCB technologies, DFM, DFA, materials, stackup design rules and assembly rules Prior hands-on experience of reviewing Hardware Schematics and PCB layout on industry standard tools. Understanding, debugging and simulations of hardware design Experience with VNA and TDR measurements for PCB characterization would be a plus. Track record of new product introduction from concept, through development and production is a plus. Knowledge of the thermal analysis of the PCB hardware is a plus. Experience with channel simulations using MATLAB or ADS or other tools is a plus. Strong communication, presentation, and documentation skills, team player Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

In today s world of faster and more virtualized servers, storage, and network connections, CPUs cannot keep up with the growing network processing demands. Legacy or foundational network interface cards (NICs) may deliver efficient networking however when running demanding workloads, they cause overhead that burdens CPUs, chewing into available processing power. To deploy more advanced networking capabilities a new generation of intelligent NICs are required to deliver accelerations and additional processing power to offload CPUs. The industry-leading NVIDIA SmartNICs/DPUs (Data Processing Units) provide sophisticated hardware offloads and accelerated networking, storage, security, and manageability services for modern cloud, artificial intelligence, telecommunications and traditional enterprise workloads. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA SmartNICs/DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications. The NBU team in India is a new team that is growing at a fast pace. We are currently seeking an Experienced Verification Engineer with strong verification fundamentals to work in NBU ASIC team. You will join a group of hardworking engineers to implement the next innovative Networking Silicon chip. In this position, youll make a real impact in a multifaceted, technology-focused company while developing the industrys best high-speed communication devices, delivering the highest throughput and lowest latency! What you ll be doing: Be responsible for verifying the smartNIC/DPU designs, architecture and micro-architecture using advanced verification methodologies. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Use advanced verification methodologies like e-specman, SV-UVM etc. What we need to see: BS / MS (or equivalent experience) with 10+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc. ). C/C++ programming/scripting language experience desirable. Ways to stand out from the crowd: Prior experience of smartNIC and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a phenomenal teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ #LI-Hybrid

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements : Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

NVIDIA is continuously reinventing itself, with a rich history that includes inventing the GPU, which sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. The current global boom in artificial intelligence research demands highly scalable and massively parallel computation horsepower, a challenge where NVIDIA GPUs excel. As a part of NVIDIA, you will be joining a dynamic team focused on tackling difficult global challenges and amplifying human creativity and intelligence. The diverse and supportive environment at NVIDIA encourages everyone to strive for excellence and make a lasting impact on the world. NVIDIA is seeking a talented ASIC STA Engineer to join the Networking Silicon engineering team. In this role, you will contribute to the development of high-speed communication devices, ensuring the highest throughput and lowest latency for AI platforms. You will work on designing innovative large-scale chips and collaborate in a professional environment where your contributions matter. Key Responsibilities: - Lead full chip and/or chiplet level STA convergence from initial stages to signoff. - Contribute to top-level floor plan and clock planning. - Optimize CAD signoff flows and methodologies. - Integrate digital partitions and analog IPs timing, provide feedback to PD/RTL, and drive convergence. - Collaborate closely with logic design and DFT engineers to define and implement constraints for various work modes efficiently. Requirements: - B.Sc./M.Sc. in Electrical Engineering/Computer Engineering. - 3-8 years of experience in physical design and STA. - Proven expertise in RTL2GDS and STA design and convergence. - Familiarity with physical design EDA tools (e.g., Synopsys, Cadence). - Hands-on experience with STA using Synopsis Primetime. - Strong understanding of timing concepts and a collaborative team player. At NVIDIA, we have a team of forward-thinking individuals who are passionate about pushing boundaries. If you are a creative engineer who enjoys challenges and is ready to grow professionally, come be a part of our industry-leading physical design team. JR1995153,

Qualcomm India Private Limited is looking for a Hardware Engineer with over 12 years of experience in SoC design. You should have a strong understanding of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. Knowledge of memory controller designs and microprocessors would be an added advantage. In this role, you will be responsible for constraint development and timing closure, working closely with SoC verification and validation teams for pre/post Silicon debug. Hands-on experience in Low power SoC design is required, along with expertise in Synthesis and understanding of timing concepts for ASIC. You should also have experience in Multi Clock designs and Asynchronous interface. Familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is necessary. Minimum qualifications include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of Hardware Engineering experience, or a Master's degree in the same field with 5+ years of experience, or a PhD with 4+ years of experience. If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. For reasonable accommodations, you may contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing agencies and individuals represented by agencies are not authorized to use this site. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

As a Design Verification Engineer, you will be responsible for verifying complex designs such as accelerators, datapath IP, processor core subsystems, and complex interfaces/protocols using leading-edge methodologies like UVM and Formal DV. Your role will involve architecting the testbench, developing the verification environment, and defining test plans, tests, and verification methodology for block/sub-system level verification. You will collaborate with the design team to generate test plans, ensure code and functional coverage closure, integrate block testbenches at the sub-system level UVM environment, and verify integration. Additionally, you will interact with the analog co-simulation and firmware team to enable top-level chip verification aspects. Your responsibilities will also include packaging verification environments for Digital IP for seamless integration into the verification flow at different stages of execution. You will evaluate 3rd party IPs on key qualitative aspects and establish evaluation flows for home-grown and 3rd party IPs for consistent benchmarking of DV evaluation. To excel in this role, you should have a minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science and 7-10+ years of experience in design verification with UVM and constrained random, coverage-based verification approaches. You must possess a strong understanding of DV concepts and the ability to develop scalable DV environment architecture for achieving first-pass DV success. Your adaptability to learn end application/systems and map them into smart verification test plans will be crucial. Excellent debugging and analytical skills, along with good interpersonal, teamwork, and communication skills, are essential for effectively driving discussions with geographically dispersed teams. Knowledge of assertion-based formal verification, standard on-chip interfaces, processor/SoC architecture, and/or DSP fundamentals will be advantageous. Experience with ASIC/SoC product DV and productization is highly desirable for this role.,

Role & responsibilities Strong verification expertise using Verilog and SystemVerilog, with solid understanding of UVM methodology and hands-on experience writing test-benches. Proficient in debugging testcases and verifying processor-based subsystems. Knowledge of AMBA protocols (AXI, AHB, APB) is a plus. Exposure to Arm-based SoCs and strong grasp of digital design fundamentals. Experience with scripting in Perl, TCL, Make, and Shell.

. Location: Bangalore/Kolkata Experience: 3+ years Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 3+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required WHERE WILL YOU DO YOUR BEST WORK

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary power control signals integration. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Your Profile You are best equipped for this task if you have: Must have worked in ASIC Design flow, with ASIC experience of upto 5years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

We are looking for a highly skilled Senior RTL Design Engineer with 8+ years of experience in designing complex digital IPs and SoCs. The ideal candidate should have strong RTL coding, micro-architecture, and synthesis knowledge, with a proven track record of successful tape-outs. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog based on micro-architecture specifications Work on design partitioning, clock domain crossings, and low-power techniques Collaborate with verification, physical design, and DFT teams across the design cycle Perform lint, CDC, and synthesis with timing constraints Optimize design for area, performance, and power Participate in design reviews and documentation Requirements: 8+ years of RTL design experience in ASIC/SoC development Strong knowledge of digital design principles and SoC architecture Hands-on experience with RTL design tools (SpyGlass, Design Compiler, etc.) Experience with AMBA protocols (AXI, AHB, APB), FIFOs, arbiters, and bus interfaces Exposure to synthesis, STA constraints, and backend handoff Strong debugging, problem-solving, and communication skills How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

SMTS SILICON DESIGN ENGINEER (AECG ASIC PD FCL Lead) T HE ROLE : We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. K EY RESPONSIBLITIES : Handling SOC floorplanning/Partitioning, Die size estimation Experience on abutted and non-abutted designs Handling of Hierarchical designs (Subfcs), Block partitioning, block pin placement, Feedthrough punching, HFN implementation Planning clock Mesh/Tree at SOC/Sub System level Full SOC bump planning including GPIO Bump Placement, Pad ring generation/GPIO placement, Hard IP bump placement, GPIO and PG RDL routing Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams P REFERRED EXPERIENCE : 12+ years of professional experience in physical design, preferably ASIC designs. Knowledge on bump placement/critical IP placement. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4

NVIDIA has been transforming computer graphics, PC Gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s motivated by great technology and amazing people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. The HWPM Team at NVIDIA is seeking an excellent ASIC Senior Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world. What You ll Be Doing: Play a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA s industry-leading SoCs and GPUs. Develop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality. Design and implement reusable, scalable testbenches and testbench components using System Verilog and UVM. Collaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure. What we need to see: M. Tech. (or equivalent) in VLSI or Electronics Engineering with 2+ years of relevant industry experience OR B. Tech with 4+ years of experience in a similar domain Proven experience in unit, sub-system or SoC Level Verification Hands-on expertise in building and maintaining testbench environments for both unit and system-level verification Proficiency in Python or industry-standard scripting languages for automation and test development Strong debugging and analytical skills Familiarity with industry-standard design and verification tools like VCS, Xcelium, etc. Solid understanding of RTL Design Principles and Verilog Experience with UVM (Universal Verification Methodology) is a strong plus Excellent communication & collaboration skills, with ability to work effectively across cross-functional teams Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, we have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you! #LI-Hybrid

Apply to this job We are looking for a highly skilled and experienced DFT Engineer to become part of our team. Our DFT Engineers will build efficient System on Chip (SoC) and IP for data center applications. This role offers the opportunity to work with industry-standard Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687) while contributing to cutting-edge technology. This role includes developing and applying DFT strategies for complex mixed-signal integrated circuits (ICs), ensuring fault coverage and testability. ASIC Implementation, DFT Engineer Responsibilities Develop and implement DFT strategies for mixed-signal ICs, considering factors such as fault coverage, test time, and in-system test Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement Generate high-quality test patterns using automated test pattern generation (ATPG) tools Verify the correctness of DFT implementation through simulation and hardware testing Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process Minimum Qualifications Bachelors degree in Electrical Engineering or Computer Engineering 6+ years of experience in DFT for mixed-signal ICs Understanding of DFT concepts, including scan insertion, BIST, and boundary scan In-depth knowledge of DFT EDA tools (Siemens/Synopsys) Familiarity with IEEE standards 1149, 1500, and 1687 Experience with fault simulation and coverage analysis tools Problem-solving and analytical skills Strong communication skills Experience of consistently working under your own initiative, seeking feedback and input where appropriate Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation Preferred Qualifications Masters degree in Electrical Engineering or Computer Engineering 10+ years of experience in DFT strategies implementation and development for mixed signal ICs Experience with mixed-signal DFT methodologies Knowledge of scripting languages (e.g., Perl, Python) for automation Experience with hardware testing and debugging About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

THE ROLE: We are seeking an engineer to join our team that will thrive in a fast-paced work environment, usingeffective communication, problem-solving and prioritization skills. Individuals that are well organized, show great attention to detail, and employ critical thinking are well-suited for our team.?? THE PERSON: Senior Member Technical Staff (SMTS) Embedded Software (Data Center & SPSE) AMD India (SPSE) is looking for a strong technical leader to lead an Embedded Software development team to lead and deliver modular, quality oriented, and extensible FW infrastructure. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. Closely collaborate with peer development and QA teams, architecture, customer support and product line management. As a key member of the Technical management staff, contribute to the vision and strategy of continuous integration, improved development processes, quality and productivity improvements.? KEY RESPONSIBILITIES: Lead and drive the Embedded software development for all new and sustaining AMD EPYC Server, DC GPU Products. Responsible for Architecture, Design, Development and Mentoring team members to become successful at AMD. Responsible for partnering leveraging all the development work done by Core engineering in Client and Embedded teams, with a strong focus on enabling differentiating features for the success of Server Business. Partner with Platform team to bring-up the AMD Security processor firmware during SOC bring-up. Partner with HW and Silicon validation teams for verification of allfeatures in the Silicon IP. Support the triage and debug of critical bugs from AMD security processor firmware side that require multi-team interactions. Support field requests / escalations from Customer application engineering team. Influence and support software engineers with design reviews, code reviews, and licensing reviews for open source as well closed source code offerings. Train and enable Applications Engineers and FAEs on software solutions with esp. focus on AMD differentiated features and technologies Provide product and technology feedback and consultancy into Enterprise product management, Enterprise Server Systems and SW efforts, and AMD technology and product planning Work on software POCs (Proof of Concepts) for early enablement of new technology. PREFERRED EXPERIENCE: Exposure to systems architecture Solid programming skills in C experience or a strong desire to learn secure coding processes and basics of encryption technology are essential. Experience with source control systems such as git Industry experiences developing embedded firmware or device drivers. Experience with JTAG debuggers and other tools. Experience with pre-silicon development on FPGAs , microntrollers or simulation environments Experience with processor, board, or ASIC bring-up. An understanding of embedded firmware or device driver development. An understanding of assembly level programming and optimizations. An understanding of PCIe, SPDM, Virtualization, and IOMMU Experiences working with RTOS and other embedded OS environments. ACADEMIC CREDENTIALS: Bachelor'sorMaster's in ElectricalEngineer, Computer Engineering, ComputerScience,or a closely related field

THE ROLE: The person will be part of AMD's CPU Performance Validation team. This team is part of AMD's global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It's always We before Me in the team KEY RESPONSIBILITIES: Responsible for building infrastructure for performance verification and verify performance of X86 processor. Writing specific targeted tests to measure the performance of the processor Involves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for CORE or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation PREFERRED EXPERIENCE: Experience: 3-15 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevantresearch and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work

The SOC RTG team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies. THE PERSON: Must have good communication & analytical thinking skills Detail oriented with strong analytical and debugging skills Experience between 7 to 13 years. KEY RESPONSIBILITIES: Integrate AMD internal IPs RTL/DV environments into SoC Debug function/performance of Graphics, Display, SMU IPs Engage with IP and SOC teams to drive closure to IP RTL deliverables. Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation Drive design and methodology improvements across teams to improve overall program execution PREFERRED EXPERIENCE: Proficiency with Verilog/VHDL RTL design languages ASIC DV experience in reusable verification methodology such as UVM Knowledge of chip bus interfaces such as AHB, AXI and various standard peripherals & interfaces is preferred. Have hands-on experience in chip level Design/Integration activities Have knowledge of SOC design specification, architecture and micro-architecture, Knowledge of various IP protocols is a plus.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SOFTWARE DEVELOPMENT ENGINEER - (EDA Development / C++ Engineer) LOCATION : Hyderabad & Bangalore THE ROLE: AMDis looking foraninfluentialsoftware engineerwho ispassionate about improving the performance of keyapplications and benchmarks . You will be a member of a core team ofincredibly talentedindustry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: B.E/B.Tech/B.S or M.E/MS in CS, EE or CE with 8+ years of software development experience Strong C++ Development background and exposure to large design patterns based codebase Background in EDA tools preferred Demonstrated proficiency in scripting using Python Excellent problem-solving skills and willingness to think outside the box Experience with production software quality assurance practices, methodologies, and procedures Excellent communication skills and experience working with global teams Work with AMD's architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and developnew groundbreakingAMDtechnologies Participating in newASICand hardware bring ups Debugging/fixexisting issuesand research alternative, more efficient ways to accomplish the same work Develop technical relationships with peersandpartners PREFERRED EXPERIENCE: Strong object-oriented programming background in C++ Ability to write high quality code with a keen attention to detail Experience withmodern concurrent programming and threading APIs Experiencewith Linux operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communicationand problem-solving skills Motivatingleaderwith good interpersonal skills ACADEMIC CREDENTIALS: Bachelor's or master's degree in computer science, Computer Engineering, Electrical Engineering, or equivalent