776 Asic Jobs - Page 4

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: The person will be part of AMD's CPU Performance Validation team. This team is part of AMD's global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It's always We before Me in the team KEY RESPONSIBILITIES: Responsible for building infrastructure for performance verification and verify performance of X86 processor. Writing specific targeted tests to measure the performance of the processor Involves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for CORE or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation PREFERRED EXPERIENCE: Experience: 3-15 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevantresearch and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks at the IP or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Industry experience is preferred. ACADEMIC CREDENTIALS: Bachelor's or master'sdegree in Electronics or Electrical or Computer engineering

As a Semiconductor Sales/Business Development Manager based in India, you will play a crucial role in leading and expanding semiconductor business engagements throughout the country. This position is well-suited for individuals who possess a proven track record in ASIC/SoC/IC services or product sales within the semiconductor industry. Your primary responsibilities will include owning the entire sales lifecycle, from prospecting and lead qualification to solution positioning, proposal development, and deal closure. You will be tasked with establishing and nurturing relationships with Tier-1 and Fabless semiconductor customers, while collaborating closely with internal engineering and delivery teams to craft customized solutions. With at least 5 years of experience in semiconductor industry sales and a focus on working with semiconductor services or product companies, you will be expected to bring a hybrid sales approach that combines both hunting (acquiring new clients) and farming (growing existing accounts). Your expertise in Semiconductor Design and end-to-end ASIC turnkey solutions will be instrumental in delivering comprehensive services ranging from Specifications to Silicon, encompassing spec definition, RTL, physical design, verification, DFT, and tape-out support. The ideal candidate for this role will possess a deep understanding of ASIC/SoC design lifecycles and semiconductor engagement models, along with a demonstrated ability to establish new accounts and expand existing ones. You should feel comfortable engaging with technical and business stakeholders, such as engineering and procurement teams, and have familiarity with turnkey project delivery or IP/ASIC services sales. This challenging yet rewarding position offers significant ownership in shaping the semiconductor sales footprint of our organization. If you are passionate about building strong customer relationships and delivering high-value technical solutions, this role presents an exciting opportunity for professional growth. If you are interested in this role or know someone who might be a great fit, please reach out via email to ranjith.allam@cyient.com.,

You are looking for a dynamic and experienced Director to lead the ASIC/SoC Division at ATRI Solutions. In this role, you will be responsible for both strategic and operational tasks, including building and scaling engineering teams, delivering pre- and post-silicon services, and fostering partnerships with leading silicon companies. Your key responsibilities will include owning and expanding a suite of engineering services such as ASIC/SoC RTL design, FPGA prototyping, board bring-up, firmware development, and embedded software. You will also need to develop asset-light delivery models using remote labs and cloud infrastructure, define engineering quality standards, and enforce automation frameworks for scalable delivery. Additionally, you will be leading ecosystem partnership programs with ASIC/SoC design houses, FPGA/EDA vendors, and cloud toolchain providers. Your role will involve establishing joint solutions, co-development programs, and representing ATRI in alliance events and technical steering groups. As a Director, you will recruit, develop, and manage engineering teams in Pune and Ahmedabad, driving cross-functional collaboration and establishing training frameworks for continuous upskilling. You will also ensure high-quality, on-time delivery across all programs, oversee project execution, and work with sales teams to shape SOWs and resource plans for client engagements. To qualify for this role, you should have at least 8 years of experience in ASIC, SoC, FPGA, or embedded systems engineering, with a background in board bring-up, silicon validation, firmware development, and FPGA-based system prototyping. A degree in Electrical, Electronics, or Computer Engineering is required, along with proven leadership skills and a track record in ecosystem development. Preferred qualifications include experience with global ASIC/SoC vendors, familiarity with tools such as JTAG and oscilloscopes, knowledge of cloud-based validation and CI/CD pipelines, and exposure to automotive, networking, AI hardware, or consumer silicon platforms.,

About Marvell Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is a leading provider of innovative technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets, providing complete solutions including controllers, product firmware, and reference board designs. Many of the same technologies have been utilized in Marvell system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect Technical leader on a fast-paced project team of R&D engineers involved in the development of cloud Datacenter products of Marvell packet processors family. Contribute to and lead all phases of software development from requirement gathering through architect/design, implementation, UT/Functional testing and maintaining multiple software components. Contribute to the development of aggressive project goals and schedules. Demonstrate technical leadership and execute projects across a highly distributed engineering team. Co-ordinate and work with various cross-functional groups such as Architect, other development teams, QA/Validation, System Test, Product Management, Product Documentation, Customer teams Responsible to mentor and train the team Provide necessary support with customers using our solutions. What Were Looking For Bachelor s/Masters in computer science/ECE with 5 to 20 Years of relevant experience. Extensive technical depth in L2 and L3 Ethernet switching and routing protocols. Extensive experience in programming languages such as C/C++/Python Extensive experience in SDK development in Switching/Routing ASIC Hands on experience on switch/router embedded system software development Experience architecting innovative, scalable Linux based Embedded products. Ability to communicate technical concepts to a wide range of audiences spanning executives to junior engineers Proven ability to successfully lead distributed teams and run projects across multiple locations Working experience in L2 switching/forwarding areas such as LAG, VLAN, xSTP, LLDP, Link OAM, ARP, VxLAN, DC fabric switching, etc Working experience in L3 unicast/multicast routing protocols such as RIP, OSPF, IGMP, BGP, ISIS, etc Working experience in areas like ACL, QoS, Policers, TCAM, etc Experience in Linux kernel, SERDES, board bring up etc. Excellent written and verbal communication skills with the ability to present complex technical information in a clear and concise manner to a variety of audiences. Ability to work independently with minimal guidance. Ability to grasp new requirements and solutions based on customer/industry needs Work cohesively in team environment and with geographically disperse teams. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1

"> Search Jobs Find Jobs For Where Search Jobs Staff RTL Design Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12211 Remote Eligible No Date Posted 21/07/2025 Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Experience Required: Expertise and strong hands-on experience in RTL design using System Verilog or VHDL Digital system architecture, Processor subsystem architecture and block definition Experience working on complex SoCs RTL design quality analysis Lint, CDC, RDC Good understanding of digital design Synthesis, DFT and Static Timing Analysis Basic understanding of mixed-signal designs Experience with gate level simulations and debug Experience in digital verification is a plus Strong written and verbal communication skills Immediate joiners only

As one of the world s leading asset managers, Invesco is dedicated to helping investors worldwide achieve their financial objectives. By delivering the combined power of our distinctive investment management capabilities, we provide a wide range of investment strategies and vehicles to our clients around the world. If youre looking for challenging work, smart colleagues, and a global employer with a social conscience, come explore your potential at Invesco. Make a difference every day! Job Description Job Description Responsible for the day-to-day activities of reporting, reconciliations, and exception monitoring Knowledge on various trading instruments and thorough understanding of the Trade operations function Analyse reconciliation results, investigate issues highlighted in regard to trade and transaction reporting breaks to ensure completeness and accuracy of reporting Ensure timely escalations are done for issue encountered while performing BAU activities Develop and maintain relations with regional stakeholders as well as various business areas Contribute to overall team progress via team meetings / ideas / initiatives / training and development. Ability to document the procedures, develop training plans and other business process relevant documentation. To deal with ad hoc activities and maintaining information systems Work Experience/Knowledge: 2 years of experience in Regulatory Reporting (MiFID, EMIR, ASIC and SFTR) is required Preferred technical knowledge on DTCC. Preferred knowledge of regulation guidelines and Kaizen Knowledge of various security types and instruments used in the industry Formal Education: Graduation/Post Graduation in Commerce/Business Administration Skills/Competencies/Attributes: Team player Knowledge of Investment Management industry, various security types and instruments Understanding of various Derivative instruments is desirable Strong Accounting skills Strong communication skills (verbal/written) Proven ability to work under pressure and meet strict deadlines Excellent interpersonal skills Flexible team player and ability to multitask and flexible to work additional hours, when needed. Proven ability to work accurately. Why Invesco What s in it for you Our benefit policy includes but not limited to: Competitive Compensation Flexible, Hybrid Work 30 days Annual Leave + Public Holidays Life Insurance Retirement Planning Group Personal Accident Insurance Medical Insurance for Employee and Family Annual Health Check-up 26 weeks Maternity Leave Paternal Leave Adoption Leave Near site Childcare Facility Employee Assistance Program Study Support Employee Stock Purchase Plan ESG Commitments and Goals Business Resource Groups Career Development Programs Mentoring Programs Invesco Cares Dress for your Day

We are looking for experienced FPGA Verification Engineer. As a FPGA Verification Engineer, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. As an FPGA Verification engineer, you will be responsible for designing verification plan, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and strong will to drive for solutions. Education Necessary: Candidates must have a bachelors degree or higher in EE with very good academics. Roles & Responsibilities: Must have 10 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take own initiatives. Highly motivated team player. We offer: A high pace in development of new products. Tight cooperation with other disciplines. Short product development cycles, Real results of your work, you will see how it affects our products and sales. International possibilities of development and internal advancement. Social and wellness activities and clubs. A friendly and helpful atmosphere. Highly competent and motivated colleagues.

THE ROLE: AMD is looking for a talented leader to help develop innovative solutions and software features, bring up new products, and improve the quality of our existing software. THE PERSON: We seek a hands-on leader responsible for a large functional area with the Software Development team. They will lead the team, planning software development projects, creating documentation, and delivering software products for internal and external customers. Requires experience with cross-team management. This role also requires that the individual can lead and interact and work with their counterparts globally to ensure effective delivery of the projects: strong Interpersonal, verbal, and written skills and the ability to multitask. KEY RESPONSIBILITIES: Participate and play a critical role in planning project deliverables Own and drive software design, development, verification, and release the product to customers Performing individual goal planning and evaluation per AMD policies Maintaining the health and morale of the team Develop and grow the engineering skills of the team Drive critical issues and interface with cross-functional teams Provide periodic management/executive updates Lead brainstorming sessions Establish the roadmap and vision for RCCL and associated communication libraries by taking into account industry trends, customer requirements particularly in high-performance computing (HPC) and deep learning and the latest developments in GPU and networking technologies Guide the design, development, and optimization of RCCL features, focusing on performance, scalability, and ease of use across various AMD platforms and interconnects (PCIe, Infinity Fabric,RoCEv2) Collaborate closely with other internal AMD teams (e.g., ASIC, hardware and software architecture, networking, Deep Learning framework teams, product management, and sales) to ensure holistic product development and market success PREFERRED EXPERIENCE: Experience in a hands-on software engineering, development, and/or architectural leadership role Solid knowledge of software fundamentals Strong C/C++ programming skills and operating system knowledge Embedded Programming knowledge and skills are desired Consistent record in engineering execution, delivering software on time with high quality, and achieving premium high-performance software solutions Proven track record of planning and delivering complex system software products Experience leading multiple projects with competing priorities Strong project management skills and experience with project management techniques such as scheduling, budgeting, and risk management Disciplined approach to problem solving and ability to make business decisions in a technical environment Deep expertise in high-performance computing, Deep Learning, and parallel programming models Strong understanding of GPU architectures, and communication libraries like RCCL, rocSHMEM, and MPI. Experience with various interconnect technologies (PCIe, Infinity Fabric, Infiniband/RoCEv2) and network protocols (RDMA). ACADEMIC CREDENTIALS: Bachelor s or Master s degree in a related discipline preferred

Sandisks High-Performance Computing environments are key to bringing new storage solutions to market. As a Senior High-Performance Computing (HPC) engineer in the IT Infrastructure team, you will be at the heart of Sandisk s engineering and product development process, delivering the IT HPC infrastructure and services that empowers engineering teams to develop new storage technologies and deliver high quality products to market quickly. As a member of the HPC as a service team HPCaaS, you will be responsible for establishing and executing strategic objectives focused on improving the effective utilization of the compute resources while meeting or exceeding customer service level agreements for job prioritization, job concurrency, and job throughput in our EDA compute clusters. This includes leading architectural innovation and path finding efforts to create and implement Sandisk s next generation Grid computing environment. As a member of the team, you will be expected to not only deliver on technical requirements and solutions but also be able to present your solutions to senior management. Responsibilities include but are not limited to working as an individual contributor, a team member and a technical team lead to explore, define, and pilot new solutions with little supervision. Develop solutions, scripts, and/or processes to automate management of services and tools as required. In this role, you will be collaborating closely with EDA and hardware design team stakeholders to define and deliver workload efficiency improvements in Sandisk s EDA HPC infrastructure globally. Role Overview: Join our global engineering product development team to support and enhance multi-site, high-performance computing (HPC) infrastructure and services. You will design, implement, and maintain automation solutions while driving continuous improvements in performance and reliability. Key Responsibilities: Manage and support distributed HPC environments across multiple locations, focusing on ASIC and GPU computing clusters. Design, deploy, and maintain Ansible automation for HPC and Unix systems. Troubleshoot complex issues within HPC clusters and file systems, performing root cause analysis and driving corrective actions. Develop and maintain comprehensive documentation for HPC infrastructure. Identify opportunities to automate repetitive tasks and improve system reliability. Recommend and implement performance enhancements for various workloads. Support a broad Engineering Design Automation (EDA) ecosystem including licensing and workflow management. Technical Environment: Workload managers: LSF, Slurm, NC EDA tools such as Cadence, Synopsys, and their workflows Automation of job submissions and workload management Monitoring and observability using Splunk and Grafana Infrastructure: RedHat/CentOS Linux, NFS storage, automounters VDI: Exceed TurboX, VNC Unix/Linux authentication integrated with Active Directory Infrastructure automation through scripting and open-source tools Qualifications Bachelor s degree in Computer Science or equivalent experience 10+ years of Linux systems administration, with strong expertise in RedHat/CentOS production environments Proven experience w

As one of the world s leading asset managers, Invesco is dedicated to helping investors worldwide achieve their financial objectives. By delivering the combined power of our distinctive investment management capabilities, we provide a wide range of investment strategies and vehicles to our clients around the world. If youre looking for challenging work, smart colleagues, and a global employer with a social conscience, come explore your potential at Invesco. Make a difference every day! Job Description Job Description Responsible for the day-to-day activities of reporting, reconciliations, and exception monitoring Knowledge on various trading instruments and thorough understanding of the Trade operations function Analyse reconciliation results, investigate issues highlighted in regard to trade and transaction reporting breaks to ensure completeness and accuracy of reporting Ensure timely escalations are done for issue encountered while performing BAU activities Develop and maintain relations with regional stakeholders as well as various business areas Contribute to overall team progress via team meetings / ideas / initiatives / training and development. Ability to document the procedures, develop training plans and other business process relevant documentation. To deal with ad hoc activities and maintaining information systems Work Experience/Knowledge: 2 years of experience in Regulatory Reporting (MiFID, EMIR, ASIC and SFTR) is required Preferred technical knowledge on DTCC. Preferred knowledge of regulation guidelines and Kaizen Knowledge of various security types and instruments used in the industry Formal Education: Graduation/Post Graduation in Commerce/Business Administration Skills/Competencies/Attributes: Team player Knowledge of Investment Management industry, various security types and instruments Understanding of various Derivative instruments is desirable Strong Accounting skills Strong communication skills (verbal/written) Proven ability to work under pressure and meet strict deadlines Excellent interpersonal skills Flexible team player and ability to multitask and flexible to work additional hours, when needed. Proven ability to work accurately. Full Time / Part Time Full time Worker Type Employee Job Exempt (Yes / No) No Workplace Model At Invesco, our workplace model supports our culture and meets the needs of our clients while providing flexibility our employees value. As a full-time employee, compliance with the workplace policy means working with your direct manager to create a schedule where you will work in your designated office at least three days a week, with two days working outside an Invesco office. Why Invesco In Invesco, we act with integrity and do meaningful work to create impact for our stakeholders. We believe our culture is stronger when we all feel we belong, and we respect each other s identities, lives, health, and well-being. We come together to create better solutions for our clients, our business and each other by building on different voices and perspectives. We nurture and encourage each other to ensure our meaningful growth, both personally and professionally. We believe in diverse, inclusive, and supportive workplace where everyone feels equally valued, and this starts at the top with our senior leaders having diversity and inclusion goals. Our global focus on diversity and inclusion has grown exponentially and we encourage connection and community through our many employee-led Business Resource Groups (BRGs). What s in it for you As an organization we support personal needs, diverse backgrounds and provide internal networks, as well as opportunities to get involved in the community and in the world. Our benefit policy includes but not limited to: Competitive Compensation Flexible, Hybrid Work 30 days Annual Leave + Public Holidays Life Insurance Retirement Planning Group Personal Accident Insurance Medical Insurance for Employee and Family Annual Health Check-up 26 weeks Maternity Leave Paternal Leave Adoption Leave Near site Childcare Facility Employee Assistance Program Study Support Employee Stock Purchase Plan ESG Commitments and Goals Business Resource Groups Career Development Programs Mentoring Programs Invesco Cares Dress for your Day In Invesco, we offer development opportunities that help you thrive as a lifelong learner in a constantly evolving business environment and ensure your constant growth. Our AI enabled learning platform delivers curated content based on your role and interest. We ensure our manager and leaders also have many opportunities to advance their skills and competencies that becomes pivotal in their continuous pursuit of performance excellence. To know more about us About Invesco: https: / / www.invesco.com / corporate / en / home.html About our Culture: https: / / www.invesco.com / corporate / en / about-us / our-culture.html About our D&I policy: https: / / www.invesco.com / corporate / en / our-commitments / diversity-and-inclusion.html About our CR program: https: / / www.invesco.com / corporate / en / our-commitments / corporate-responsibility.html Apply for the role @ Invesco Careers : https: / / careers.invesco.com / india /

The ideal candidate for this role should possess a Bachelor's or Master's degree or equivalent practical experience along with a minimum of 5 years of experience in Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies. They should have a proven track record in developing DFT specifications and DFT architecture, fault modeling, test standards, and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation, and verification flow. Preferred qualifications for this position include experience with DFT for a subsystem with multiple physical partitions, Internal JTAG (IJTAG) ICL, Procedural Description Language (PDL) terminology, ICL extraction, Instrument Connectivity Language (ICL) modeling with Siemens Tessent Tool, Spyglass-DFT, DFT Scan constraints, and evaluating DFT Static Timing Analysis (STA) paths. Knowledge of coding languages like Perl or Python, as well as familiarity with DFT techniques like SSN and HighBandwidth IJTAG, are also desirable. As a part of the team responsible for developing custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation in products that are loved by millions worldwide, delivering unparalleled performance, efficiency, and integration. Google's mission to organize the world's information and make it universally accessible and useful guides our work, combining the best of Google AI, Software, and Hardware to create radically helpful experiences. In this role, you will collaborate with Design for testing (DFT) engineers, Register-Transfer Level (RTL), Physical Designer Engineers, System on a chip (SoC) DFT, and Product Engineering team. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains, writing scripts to automate the DFT flow, developing tests for Production in the Automatic Test Equipment (ATE) flow, and collaborating with the DFT team to deliver two or more Subsystems in a SoC.,

We are a leading artificial intelligence computing company and are paving the way with innovations in gaming, visualization, supercomputing, and self-driving cars. NVIDIA gives automakers, tier-1 suppliers, automotive research institutions, and start-ups the power and flexibility to develop and deploy breakthrough artificial intelligence systems for self-driving vehicles. Our unified computing architecture makes it possible to train deep neural networks in the data center on the NVIDIA DGX , and then seamlessly run them on NVIDIAs DRIVE platform inside the vehicle. Leading vehicle manufacturers, tier 1 suppliers, mapping and simulation companies, software and sensor providers, and startups around the world are developing on the NVIDIA DRIVE platform to deliver the best solutions for the new world of mobility. As a System Software Architect in the Automotive team, you will get an opportunity to work on NVIDIAs latest SOCs, help tackle complex and important problems, and work alongside industry experts in diverse teams and projects. What you ll be doing: Architect, design and develop safety (ISO26262) and security (ISO21434) compliant system software for NVIDIA DRIVE platform for autonomous vehicles Architect, design and develop Real Time System Software features for NVIDIA Tegra SOC Design & develop I/O Virtualization solutions for NVIDIA Tegra SOC Development & bring-up activities for next-generation Tegra SOC Work with the ASIC teams to enhance SW performance and virtualization support in the SOC Extensively use Formal Methods to architect and develop high integrity software Design debugging solutions and tooling to improve developer experience on DRIVE platform Learn to harness maximum and consistent system software performance and develop workflows and tools to measure performance What we need to see: Bachelors/Masters or equivalent experience in Computer Science 8+ years of experience in System Software architecture and development for real time embedded systems Strong understanding of computer architecture and operating system fundamentals Experience in designing and developing solutions for complex system problems. Strong C and/or Ada/SPARK programming and debugging skills Hands-on experience with performance analysis and system analyzer tools Strong background with debugging tools A dedicated, team and results oriented, self-motivated contributor with excellent analytical and interpersonal skills Ways to stand out from the crowd: In-depth knowledge of embedded systems and real time operating systems, like QNX and RT Linux skills Good understanding of ARM architecture and low level software development for ARM v8 based SOCs Prior hands-on experience in Ada/SPARK programming (including specification and formal verification) and TLA+ formal verification modeling Experience performing architectural safety analysis (FMEA/DFA) and security analysis (Threat modeling) Background in software development in compliance to ISO 26262 standard following Software Development Life Cycle (SDLC) practices With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most talented people in the world working for us. Do you want to be one of them? If youre creative and self driven, we want to hear from you!

Introduction Edgecortix Inc. is seeking a Hardware Design Engineer with proven RTL/logic and ASIC design expertise. If you have a strong desire to build state-of-the-art digital chips and systems join us and lets reshape the future of AI. Your Role and Responsibilities: Ideal candidates will have expertise in several of the following areas: RTL Design and module-level verification of modules for Edgecortix inference accelerator IP. Participate in synthesis, STA, and power estimation activities. Propose and implement low-level micro-architectural optimizations for better area, power, and placeability/routability of design targeting specific tech processes, power, and area budgets. Work closely with our architects to support architectural-level decisions providing expert feedback to ensure high design scalability. Collaborate with our architects and compiler engineers to determine the best way of implementing new functionality and defining architectural specs. Engage in system integration activities for SoC design using third-party IPs and integration tools. Engage in IP-level and system-level verification and debugging activities using SystemVerilog and UVM. Embrace high standards of engineering practices such as code reviews, technical documentation, propper testing process, continuous integration, and release engineering. Desired Qualifications (ASIC) Ability to write clean, readable, synthesizable RTL. Familiarity with AXI, Avalon or similar protocol. Experience in low power RTL design. Experience in performing logic synthesis using Cadence or Synopsys tools. Experience in writing timing constraints and power intent definitions. Experience in optimizing design for timing. Experience in using power analysis tools such as Joules or PowerPro. Understanding of Physical Design issues. Understanding of using fixed-point arithmetic for approximating floating-point computations. Experience with verification using SystemVerilog and UVM. Experience with DDR, PCI-E, MIPI CSI or other high speed protocols is a plus. Decent scripting and automation skills using TCL, Python, and Make. Basic programming skills in statically typed languages such as C++ or Java. What s in it for you Make a difference : you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum. Benefits and Perks Highly competitive salary and stock options Flex work time and ability to work fully remotely Support for obtaining visa and relocation support (in case of non-remote)

MTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms. You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will: Architect and implement verification environments for complex functional blocks Create and enhance verification environments using SystemVerilog and UVM Develop comprehensive test plans through collaboration with design engineers, SW and architects Implement coverage measures for stimulus and corner-case scenarios Participate in test plan and coverage reviews Drive complex RTL and TB debugs Drive UPF based low power verification Contribute to verification activities across simulation and emulation platforms Work on creating the automation scripts to support DV methodologies Create infrastructure to performs system level performance analysis Manage a team of 6-8 DV Engineers Bachelors degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks Managing a team of DV Engineers Experience with RTL development environments Proficiency in hardware description languages and verification methodologies Experience verifying complex IP blocks integrated into SOCs Knowledge of verification platforms including UVM, emulation, and FPGA Demonstrated success in test plan development and verification infrastructure Experience with industry-standard tools and scripting languages (Python or Perl) Understanding of object-oriented programming concepts Advanced degrees in Computer Science, Electrical Engineering, or related field Experience with ARM and DSP instruction set architectures Expertise in system-level debugging Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols Experience with formal verification methods Experience with Low power verification methods Experience with Baremetal processor environments Transaction level modelling expertise Familiarity with industry standard I/O interfaces FPGA and emulation platform knowledge Understanding of SoC architecture Strong verbal and written communication abilities

Where ASIC Digital Design, Sr. Architect Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12249 Remote Eligible No Date Posted 17/07/2025 Job Titles: ASIC Emulation Sr. Architect We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary and accomplished ASIC emulation expert with a passion for leading teams and solving complex challenges in digital design. Your career has been marked by a commitment to innovation, technical excellence, and driving results in fast-paced, collaborative environments. You have a proven track record of architecting and optimizing emulation solutions for high-performance, mixed-signal IPs, and thrive on guiding teams to deliver robust, scalable verification environments. Your leadership style fosters trust, encourages open communication, and empowers engineers to achieve their best. You are adept at bridging the gap between design and verification, and you excel at translating technical requirements into actionable plans. Your expertise extends to regression management, test coverage analysis, and the development of emulation-friendly models, ensuring projects are delivered on time and to the highest quality standards. You are customer-focused, comfortable representing your work to both internal stakeholders and external partners, and committed to continuous learning and professional development. Your ability to mentor, inspire, and innovate makes you an invaluable asset to any organization. If you are excited by the prospect of shaping the future of emulation at the forefront of semiconductor technology, you belong at Synopsys. What You ll Be Doing: Lead the integration of verification environments and RTL into the Zebu emulation platform for seamless operation. Execute emulation tests, debug issues, and optimize environments for improved performance and reliability. Manage and analyze regression results to identify issues and ensure comprehensive test coverage. Collaborate with design and verification teams to align requirements and resolve bottlenecks effectively. Innovate and refine emulation methodologies to enhance scalability, efficiency, and reliability. Define requirements on simulation environments to enable mapping to emulation environments. Define emulation targets and test plans to be prioritized for emulation. Develop emulation-friendly Real Number Models (RNM) for mixed-signal IPs to expedite digital and firmware verification. Define emulation planning across the IP titles, report status, risks, and mitigations to emulation plan. Standardize emulation flows across PHY and controller IPs, working closely with Synopsys Zebu team. Represent Synopsys on customer calls regarding emulation validation strategy, plans, and progress. Lead a team of emulation engineers, providing direction, mentorship, and technical leadership. The Impact You Will Have: Drive the integration of cutting-edge verification environments into emulation platforms, ensuring high performance and reliability. Enhance the efficiency of the emulation process, leading to faster and more reliable verification of complex designs. Ensure comprehensive test coverage through meticulous regression analysis and issue identification. Collaborate effectively with design and verification teams to optimize emulation strategies and resolve bottlenecks. Innovate emulation methodologies, contributing to the scalability and efficiency of verification processes. Develop and implement emulation models that accelerate the verification of mixed-signal IPs. Standardize emulation processes across various IPs, promoting consistency and best practices. Represent Synopsys in customer interactions, showcasing expertise in emulation validation. Lead and mentor a team of emulation engineers, fostering a collaborative and innovative environment. What You ll Need: 20+ years of hands-on emulation experience on platforms such as Palladium, Veloce, or Zebu. Extensive knowledge of design mapping, testbench mapping, and transactor development for emulation environments. Expertise in hardware/software debug solutions tailored to emulation, with excellent debugging skills in functional and gate-level simulations. Strong programming skills in object-oriented languages such as C++, Java, or Python, and scripting languages like PERL, TCL, and Shell scripts. Hands-on experience with verification metrics, including functional, code, and assertion coverage. Comprehensive knowledge of protocols, including PCIe, I2C, and Ethernet packet headers. Familiarity with multi-domain verification environments, SystemVerilog DPI, and collaborative workflows using Git, Jenkins, or CI/CD pipelines. Strong analytical and problem-solving skills, with a proven ability to mentor junior engineers and collaborate effectively. Who You Are: A strong leader with excellent communication and mentoring skills. Innovative and committed to continuous improvement. Detail-oriented with a strategic mindset. Collaborative, with the ability to work effectively in a team environment. Passionate about technology and eager to work on cutting-edge projects. The Team You ll Be A Part Of: You will be part of a dynamic team focused on driving innovation and excellence in the emulation of state-of-the-art protocol IPs. The team collaborates closely with design and verification teams to ensure the successful integration and optimization of verification environments. As a key member of this team, you will lead and mentor a group of talented engineers, fostering a culture of collaboration and innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

SSD Firmware Development Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Design, implement, debug firmware for the next generation of SSDs HW Interface drivers, algorithm design and implementation Contribute to the SSD firmware and play a significant role in delivering next generation SSDs to market Work with the firmware Architects, ASIC, flash media, validation and other cross functional teams on regular basis Design and implement firmware modules, algorithms needed to achieve best in class performance goals Develop characterization and evaluation programs for new products Support failure analysis on test systems Active participation in technical design, implementation reviews across teams and functions Desired Skills & Experience BE/BTech/MTech degree or equivalent or higher with 4 or more years of related experience Excellent Embedded C programming skills is a must. Nice to have Assembly language programming skills Must have strong problem-solving skills Experience using logic analyzers and protocol analyzers is preferred Having experience with NAND flash is highly desirable but not mandatory The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment Self-motivated and self-directed, however, must have demonstrated ability to work well with people. A proven desire to work as a team member across internal and cross functional teams. Ability to work effectively cross-functionally and globally. Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadlines. Excellent communication (written and verbal) and interpersonal skills. Prior experience of design/Bring up on new generation SOC/ASIC will be a definite plus High level understanding of Storage Stack/Data path is desirable Job Category Embedded Solutions Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

RTL DESIGN LEAD ENGINEER The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks. Desired Skills and Experience- 8+ years of Experience Engineering experience with exposure to front end ASIC tool flows Should be self-driven and independent in tracking and closing tasks with respective holders. In depth knowledge of AHB and bus infrastructures like matrix and fabrics Good understanding of ARM based SoC Architecture Exposure to ARM Cortex A/M integration or support Good understanding of SoC DV methodology Good experience in Low-Power design methodology Hands-on experience with ASIC tools Lint, CDC etc System Verilog/Verilog RTL coding Power aware RTL coding/design knowledge Understanding of Clock-Structures/Scheme Good Communication Skills Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USATexas

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida