776 Asic Jobs - Page 5

We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role. Responsibilities: Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog. Create and utilize real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Take ownership of Analog/Mixed designs at the chip and/or block level, ensuring successful verification. Good Understandingof GLS simulations Collaborate with design engineers to understand design tradeoffs and create high-level models for design analysis. Perform behavioral modeling for verification simulations to validate the functionality and performance of mixed-signal designs. Debug and resolve issues arising from verification simulations and work closely with the design team to address any design-related concerns. Stay updated with the latest advancements in mixed-signal verification methodologies and tools, and drive continuous improvement initiatives. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards. Key Responsibilities: Ethernet Protocol Expertise Demonstrate expertise in Ethernet standards, encompassing 100G to 800G. In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA). Proficiency in PTP 1588 standard and various Ethernet frame types. Competence in packet insertion/extraction techniques. (Additional knowledge of AXI protocol would be considered an advantage) UVM/SV Proficiency Showcase strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Architectural Skills Proven ability to architect, build, and maintain a comprehensive verification stack. Test Development Extensive experience in developing a set of regression tests for verification purposes. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). Excellent understanding of Ethernet protocols, ranging from 100G to 800G. Proficiency in PTP 1588 standard and various Ethernet frame types. Experience with packet insertion/extraction techniques. Knowledge of AXI protocol (preferred). Proven ability to architect, build, and maintain verification stacks. Demonstrated expertise in developing a comprehensive set of regression tests. If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of cutting-edge technology, we encourage you to apply. Join our dynamic team and contribute to the advancement of next-generation technologies. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: Over 4 years Location: Bangalore Skills: Proficiency in SystemC, C++, and SV/Verilog, coupled with hands-on coding experience in these languages. Strong aptitude for debugging and effective communication. Familiarity with scripting languages (desirable). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a skilled and motivated DDR5/SerDes Verification Engineer to join our organization. As a DDR5/SerDes Verification Engineer, you will be responsible for verifying and validating the functionality and performance of DDR5 memory subsystems and high-speed SerDes interfaces. In addition to strong DDR5 and SerDes verification expertise, knowledge and experience with sideband I2C and I3C protocols would be considered a plus. Candidate should have Design and implement advanced verification environments and test benches using SystemVerilog/UVM Experience4-10 Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: 8+ years Location: Bangalore/Hyderabad Skills: Profound expertise in MACSec and Ethernet technologies. MACSec (Media Access Control Security): Proficient in point-to-point security implementation on Ethernet links, adhering to the IEEE 802.1AE-2018 standard. IPsec (Internet Protocol Security): Skilled in establishing security between two devices across an Internet Protocol network. Hands-On Knowledge: Proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), with practical experience in their application. Testbench Development: Demonstrated experience in developing comprehensive Test Benches (TB) and individual verification components. Communication and Leadership: Possesses excellent communication skills and adept at leading and coordinating teams effectively. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic blocks and modules in accordance with project specifications and quality standards. Utilize your expertise in ARM Micro Architecture to optimize and enhance design efficiency. Perform RTL simulations and conduct thorough functional and timing analysis. Identify and resolve design issues, ensuring the delivery of high-quality RTL designs. Stay up-to-date with industry trends and emerging technologies to continually improve design methodologies. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience as an RTL Design Engineer with 7 to 20 years of relevant work experience. Strong knowledge of ARM Micro Architecture and its application in RTL design. Proficiency in RTL design tools and methodologies. Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS). Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work effectively in a dynamic and fast-paced environment. If you are a highly motivated and experienced RTL Design Engineer with a passion for innovation and a strong background in ARM Micro Architecture, we encourage you to apply for this exciting opportunity. Join our team and contribute to the development of cutting-edge technology solutions. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities: IP and SOC Verification Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes. Gate-Level Simulation (GLS) Proficiency in Gate-Level Simulation is a mandatory requirement for this position. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Proficiency in Gate-Level Simulation (GLS). If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes. CDP, GDP, DFT DV Expertise Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies. Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM). Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM. If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Redefine how verification is done!Were hiring Functional Verification Engineers for Bangalore to tackle IP/SoC verification, cache coherency, and more.Experience Required4"“18 YearsKey Skills: High-speed protocols, low-power simulations (UPF), System Verilog/UVMBe a part of the innovation journey! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Job Title: ASIC RTL Design Engineer Position Experience Level: 6 to 10 years Location: Bangalore : We are seeking a highly skilled and experienced ASIC RTL Design Engineer to join our team in Bangalore. The successful candidate will have 6 to 10 years of relevant experience and will play a crucial role in the design and integration of RTL components for complex ASIC projects. The candidate should possess a strong background in RTL UPF, SoC Design Integration, and multi-domain UPF methodologies. Additionally, a strong understanding of resolving VSI issues is required to excel in this role. Key Responsibilities: RTL UPF Experience: The ideal candidate should have a proven track record of working with RTL UPF (Unified Power Format) to efficiently manage power intent for ASIC designs. SoC Design Integration: Experience in the integration of RTL components into System-on-Chip (SoC) designs, ensuring seamless functionality and performance. Multi-Domain UPF: Proficiency in working with multi-domain UPF to address power management across different aspects of the design. VSI Issue Resolution: Ability to identify and rectify VSI (Voltage Storm Immunity) issues to enhance the reliability and robustness of the ASIC design. Additional : In addition to the core responsibilities, candidates who have experience in addressing UPF constraints and issues during the synthesis process and Engineering Change Orders (ECOs), including mitigating RTL-UPF mismatches, will be considered favorably. This position offers an exciting opportunity to work on cutting-edge ASIC projects, pushing the boundaries of design and innovation. If you are a seasoned RTL Design Engineer with the requisite experience and skills, we encourage you to apply and join our dynamic team in Bangalore. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Number of Open Positions4 Experience: 4+ years Location Hyderabad : We are looking for a highly skilled and experienced Gate-Level Simulation Engineer to join our team. The ideal candidate should have a minimum of 4 years of experience and possess a strong background in gate-level simulation (GLS). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is essential for this role. Key Responsibilities: Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry standards and best practices in gate-level simulation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in gate-level simulation. Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Prior experience in gate-level simulation is essential. Familiarity with gate-level simulation tools and methodologies. Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work in a dynamic and fast-paced environment. If you are a motivated and experienced Gate-Level Simulation Engineer with a strong background in SV, UVM, and a passion for ensuring the quality and reliability of digital designs at the gate level, we encourage you to apply for this position. Join our team and contribute to the success of our cutting-edge projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaHyderabad

Let your ideas power the next wave of technology!Were hiring Design Verification Engineers for Bangalore and Hyderabad.Experience Required4"“18 YearsKey Skills: HSIO protocols like PCIe, DDR5, HBM, USB, low-power simulationsWork on cutting-edge verification projects and take your career to new heights. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: 5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design Strong understanding of digital basics Proficiency in RTL coding (Verilog), IP design, and RTL integration Hands-on experience with LINT, CDC, and RDC Experience in writing UPFs and CLP/VCLP checks Familiarity with synthesis flow and validating design constraints Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc. Strong scripting knowledge Responsibilities: Understand the overall ASIC flow and effectively collaborate with multiple teams such as DV, DFT, Synthesis/Implementation, and PD teams Ability to take on the role of a Technical Manager while maintaining hands-on contributions NoteInterested candidates should provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad

Calling all innovators and creators!Were hiring RTL Design Engineers for Bangalore to work on complex ASICdesigns and integrations.Experience Required3"“25 YearsKey Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)Join us and design the future of technology! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

What Youll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills.

. Your Team, Your Impact The team is responsible for the post-silicon validation of high-speed transceiver ASICs for coherent optical communications within Marvell s Coherent DSP Business Unit. The team develops software validation platforms, performs post-silicon validation of hardware and firmware components of the ASIC, develops and documents user interfaces for customers, and provides technical support to Marketing, Applications, and customers. What You Can Expect The Marvell switching team is looking to hire a QA engineer whose role is to design and execute test plans and test cases that ensure the delivery of high-quality product to customer. Successful candidates must have a strong passion for the latest technologies and strong problem solving and troubleshooting skills. Work closely with peers in a team of skilled engineers designing and developing networking software for Switch Products. The candidate will participate in SDK qualifications and will work on the following areas: Design test strategy and test plan of your SDK features. Validate forwarding or Datapath features on switch ASIC. Develop automated tests in one of programming languages (preferably python). Work with architect and development team to deliver SDK release with solid quality. What Were Looking For Bachelor s/Masters degree in Computer Science, Electrical Engineering or related fields and 4-15 years of related professional experience. Good at one of programming languages (preferably python). Have experience in one or multiple of the following areas: Layer 2/Layer 3 protocols, QoS, ACL MPLS, IPinIP, VxLAN, IPGRE Tunnels Datapth features like buffer management, queueing, shaping, metering, AQM/ECN etc. A team player with good communication skills. It would be a big plus if the candidate is familiar with CI/CD tools: GitLab, Jenkins etc. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1

Senior Staff Applications Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12246 Remote Eligible No Date Posted 17/07/2025 Alternate Job Titles: Senior Staff Applications Engineer Post-Sales Application Engineer Interface IP Technical Solutions Engineer IP Integration Staff Engineer Customer Success (IP) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a deeply skilled engineering professional with a passion for enabling the success of others. You thrive in a dynamic, customer-facing environment, where your technical expertise and problem-solving abilities are tested daily. You have a strong foundation in ASIC/SoC front-end design, with hands-on experience in RTL coding, synthesis, timing analysis, and formal verification. You re adept at debugging complex designs whether in simulation, emulation, or actual silicon and you understand the intricacies of at least one industry-standard protocol such as USB. Collaboration is at the heart of your work style: you communicate effectively with both customers and internal teams, translating technical needs into actionable solutions. You take initiative, anticipate challenges, and enjoy the satisfaction of resolving tough issues. Your high degree of self-motivation, personal responsibility, and analytical rigor ensures that you deliver results even under pressure. You are eager to share best practices, drive continuous improvement, and contribute to the broader success of your team and customers alike. If you are excited about tackling new challenges, committed to excellence, and ready to make a real impact in the semiconductor industry, you will find your place at Synopsys. What You ll Be Doing: Providing expert technical support to customers integrating Synopsys Interface IPs into their SoC designs. Analyzing and resolving complex issues related to IP configuration, integration, and usage across various platforms. Interfacing directly with customers to understand their design and verification flows, identifying both current and future needs. Collaborating with cross-functional teams to address and resolve customer challenges efficiently. Debugging and troubleshooting designs in simulation, emulation, and silicon environments. Driving the adoption of best practices and lessons learned from customer interactions back into product development. Proactively engaging with customers during integration and silicon debug phases to ensure successful deployment. The Impact You Will Have: Accelerating customer time-to-market by providing timely and accurate technical guidance. Enhancing customer satisfaction and trust in Synopsys IP solutions through effective support and problem resolution. Contributing real-world feedback to product development, improving the robustness and usability of Synopsys IP. Reducing post-sales escalations and ensuring smooth IP integration for major industry players. Fostering long-term customer partnerships by consistently exceeding expectations. Helping shape the direction of next-generation IP products based on customer needs and industry trends. What You ll Need: Bachelor s or Master s Degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. Minimum 8 years of relevant experience in ASIC/SoC front-end design, including RTL coding (Verilog), logic and clock tree synthesis, static timing analysis, and equivalence checking. Full understanding of digital design methodologies and tools, including formal verification. Domain knowledge of at least one interface protocol (e.g., USB); experience with additional protocols (PCIe, DDR, SATA, HDMI, MIPI, Ethernet) is a plus. Experience supporting at least one ASIC/SoC tape-out from concept to full production. Strong silicon debug and troubleshooting skills are highly desirable. Who You Are: Technically creative, results-oriented, and able to manage multiple priorities efficiently. Strong communicator who can explain complex technical concepts to diverse audiences. High degree of self-motivation and personal responsibility. Excellent analytical, reasoning, and problem-solving skills with keen attention to detail. Collaborative team member who thrives in cross-functional environments. The Team You ll Be A Part Of: You will join the Solutions Group at Synopsys, a highly collaborative team dedicated to delivering world-class IP solutions and customer success. Working closely with experts in design, verification, applications engineering, and product development, you will be at the forefront of supporting and enabling the most innovative semiconductor companies across the globe. Our team values knowledge sharing, continuous learning, and a proactive approach to solving the industry s toughest challenges. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Ciscos core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Ciscos ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelors or a Master s Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns. Why Cisco? #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we re "old" (36 years strong) and only about hardware, but we re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don t care. Tattoos? Show off your ink. Like polka dots? That s cool. Pop culture geek? Many of us are. Passion fo Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidates hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

You are an experienced Design for Testability (DFT) Engineer who will be responsible for leading and defining the overall DFT strategy for critical ASIC and SoC projects at HCL Tech. Your expertise in DFT methodologies is crucial for driving the implementation of robust test strategies to ensure the manufacturability and high-quality testing of next-generation integrated circuits. In this senior-level role, you will collaborate with design and verification teams to seamlessly integrate DFT techniques throughout the design flow. Your responsibilities include developing and implementing advanced DFT methodologies such as scan insertion, ATPG, Boundary Scan, and Design for X to achieve exceptional test coverage and fault detection rates. You will also champion best practices for DFT, participate in design reviews, mentor junior engineers, and analyze test results to identify and address potential design issues. To qualify for this position, you should hold a Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with a minimum of 10+ years of experience in DFT for complex ASICs and SoCs. Your proven track record of successfully leading DFT strategies for high-volume production and in-depth knowledge of advanced DFT concepts are essential. Additionally, expertise in industry-standard DFT tools and scripting languages for automation, as well as a strong understanding of digital design principles and manufacturing test processes, will be beneficial. Joining HCL Tech as a DFT Engineer offers competitive salary and benefits, the opportunity to lead cutting-edge DFT strategies, a dynamic work environment with professional growth opportunities, and recognition for outstanding contributions. If you are a highly accomplished DFT Engineer looking to make a significant impact in the field of integrated circuits, this role is perfect for you.,

THE ROLE: The focus of this role in the AECG ASIC organization is to play a key role in driving project success across architecture, design, verification, and physical design. You ll collaborate with cross-functional teams, tackle different problems with diligence for next generation ASICs that meet Engineering, Business and Customer requirements with best PPA. THE PERSON: The ideal candidate will have a strong interest in Architecture, Digital Logic Design and Verification, Design for Test, Synthesis, Static Timing Analysis, Power Verification and optimization, Physical Design aspects like Floorplan, Full chip timing, Place and Route and Utilization experiments. While we do understand that it is very difficult to have knowledge on expected areas, the candidate should have strong foundation in digital design to pick up the necessary concepts and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or any pre-silicon technical issue. You should be able strike a balance between collaborative problem-solving and independent solution development. KEY RESPONSIBILITIES: Study both high-level and micro-architecture specifications to gain an in-depth understanding of new features or changes proposed in new projects. Developing micro-architecture specifications and refining execution methodologies for cutting-edge chip designs. Work with Architecture/RTL/DFT teams for having optimal design. Technical lead on AECG ASIC solutions, tackling problems across domains with focus on driving the best Power, Performance, Area with quality silicon for customers. Manage and monitor changes in the given tasks as project matures and be quick to re-align with new or different requirements. Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase. Work with technology/PD teams to drive signoff margins, reliability related analysis for ASIC use cases. Develop technical relationships with broader AMD Design/CAD community and peers. PREFERRED EXPERIENCE: Strong understanding of development of custom ASICs for external customers. Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design. Strong understanding of SoC Architecture and Digital Design concepts. Strong background in STA, Clocks and Power optimization techniques. Experience with Verilog or SystemVerilog and UVM Knowledge of power management, boot, CPU, AXI Interconnect and I/O peripherals Knowledge of PCIE, JESD, CPRI Understanding in physical design for PPA optimization. Proven track record of delivering SOCs in process technologies 7nm and below. Experience in leading a small team of high performing individuals. EDUCATION & EXPERIENCE: Bachelors or Masters degree in in Electrical Engineering or Computer Science. 15+years of experience in ASIC development. LOCATION: Bangalore #LI-RP1

About the Company: Founded with the vision of building a runtime reconfigurable, future-proof processor, Morphing Machines is a fabless semiconductor company working on a ground-breaking technology that will transform the chip design landscape. Morphing Machines patent protected IP, REDEFINE, can concurrently accelerate heterogenous workloads, on a homogenous fabric of processing cores. REDEFINE combines ASIC (Application Specific Integrated Circuit) like performance with the reconfigurability of FPGAs (Field Programmable Gate Arrays). Morphing Machines innovation enables dataflow compute, which is a paradigm shift in the current processor industry. Due to the nature of our architecture, we can cater across domains from Data Centers, Quantitative Finance, AI/ML acceleration, Edge Vision to High Performance Compute (HPC) applications, all with the same hardware fabric. At Morphing Machines, we are building a cutting-edge technology guided by our vision to build truly software-defined hardware. Job Overview: We are seeking a skilled FPGA Engineer who will drive the emulation of our REDEFINE dataflow accelerator on cloud-based Xilinx FPGA platforms and physical FPGA boards. This is an exciting opportunity to work at the intersection of cutting-edge FPGA technology, cloud platforms, and hardware-software co-design. Key Responsibilities : FPGA Emulation Development Design, implement, and optimize FPGA-based emulation environments for the REDEFINE dataflow accelerator. Develop FPGA design and RTL code for various hardware system and sub-system configurations. Integrate and simulate the emulation environment to validate the functionality and performance of the accelerator. Collaborate closely with hardware and software teams to ensure accurate architectural representation in emulation. Work with RTL verification teams to identify and resolve design issues using simulation and debug tools. Document and report emulation results, test findings, and recommendations to the broader engineering team. Cloud-Based Xilinx FPGA Platform Integration Configure and deploy the REDEFINE dataflow accelerator on cloud-based Xilinx FPGA platforms (e.g., Amazon EC2 F1 instances, Xilinx Alveo cards). Optimize and fine-tune the emulation environment for high performance on cloud FPGA platforms. Collaborate with software teams to integrate the software stack into the cloud-based emulation environment. Required Skills & Experience : Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience as an FPGA Engineer specializing in emulation and validation. Strong expertise in FPGA design, implementation, and verification using Xilinx FPGAs and Vivado tools. Experience with cloud-based FPGA platforms such as Amazon EC2 F1 or Xilinx Alveo. Proficiency in RTL coding (VHDL or Verilog). Knowledge of RISC-V architecture and dataflow accelerators (preferred). Familiarity with FPGA debugging tools and methodologies. Strong analytical and problem-solving skills. Excellent communication and teamwork abilities. Self-motivated, detail-oriented, and passionate about working on innovative technologies. What We Offer : The opportunity to contribute to the emulation and validation of a novel, many-core dataflow accelerator targeting next-generation high-performance systems. A collaborative work environment with talented teams across hardware architecture, system software, and FPGA engineering. Exposure to advanced FPGA technology, cloud deployment at scale, and the design flow leading up to GDS-II. Apply Now

Meet the Team The Cisco Distributed System Engineering (DSE) group is at the forefront of developing products that power the largest networks in the world. The networking industry is going through a massive transformation to build the next generation infrastructure to meet the needs of AI/ML workloads and continuously increasing internet users and application. We are uniquely positioned to capture that market transition. This team builds products by harnessing the potential of open-source technologies while pushing the boundaries on Systems and Silicon Architecture. They are the developers and leaders who are passionate about tackling complex technology, building large scale distributed systems and comfortable working with open-source communities and technologies. Your Impact You will be involved with a fast-paced work environment and responsible for end-to-end product development and production support. Software Development Integration: Develop and maintain platform adaptation layers for seamless integration between SONiC and underlying hardware (e.g., ASICs, BMC, and other platform elements). Write, review, and optimize code for critical system modules, drivers, and APIs supporting high-performance data planes and control planes. System Design: Work with Technical Leader on the technical architecture to integrate SONiC with platform infrastructure, ensuring scalability and high availability. Design robust interfaces between SONiC and platform-specific management/control modules (e.g., telemetry, diagnostics, and security components). Collaboration Engagement: Collaborate with product management and customers to understand use cases, gather requirements, and align deliverables with business objectives. Evaluation and adoption of new tools, technologies, and methodologies to accelerate development and testing cycles. Participate in code reviews, technical discussions, and issue resolution to ensure timely and quality deliverables. Minimum Qualifications 5-8 years of experience in software development within the networking or telecommunication industry. Software development experience with Linux based platforms or other like network operating systems such as SONiC. Experience with platform infrastructure such as ASIC drivers, NPU, BMC, Optics and network OS development. Experience working with virtualization, containerization, and orchestration frameworks such as Docker, Kubernetes and/or similar. Experience working on technical projects in a complex development environment. Preferred Qualifications Experience with platform level security requirements and compliance frameworks. Understanding of telemetry systems and software-defined networking (SDN). Exposure to SONiC or experience working with the SONiC open-source community. Knowledge of hardware abstraction layers and SDKs from major networking silicon providers (such as Broadcom, Marvell, Mellanox etc). #WeAreCisco (This is the Standard and cannot be changed) #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection we celebrate our employees diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer 80 hours each year allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us! Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidates hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

Staff Systems Engineer, WiFi/Bluetooth in Bangalore, India Staff Systems Engineer, WiFi/Bluetooth Description Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra AI-Native embedded compute, Veros wireless connectivity, and multimodal sensing solutions. We re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play. Synaptics is looking for Sr. Staff Systems Engineer, WiFi/Bluetooth to join our dynamic and growing organization. You will be responsible for developing and driving new technologies working on the PHY algorithm development, system integration, and working with RF/CHIP/SW team in validating and optimizing overall performance of connectivity chips. This position reports to the Director, WLAN System Algorithms and Architecture. Responsibilities & Competencies Job Duties Be involved in the algorithmic partition across software, firmware and hardware Lead development of connectivity PHY baseband algorithms and new features in wireless system that enhance system performance or reduce cost and die-size Be closely involved in the standardization activities in IEEE /WFA/or BT SIG Partner closely with RF, ASIC and SW teams to implement algorithms in the hardware/firmware Function as a highly skilled individual contributor and provide technical guidance in the systems design team Work closely with RF, Software, Algorithm, Chip, AE/FAE, Marketing teams for productizing WLAN&BT Combo chip for Home IOT and Automotive markets Competencies Strong research and development background in wireless technologies Track record of taping out multiple chips Proactive, self-starter, able to work independently in a fast-paced environment Well organized with strong attention to detail; proactively ensures work is accurate Positive attitude and work ethic; unafraid to ask questions and explore new ideas Ability to become part of and lead geographically distributed, cross functional project teams as necessary Resourceful and able to solve problems through adapting technology and a solid understanding of product architecture Analytical and able to make informed decisions based on experience Sets clear expectations and objectives, and brings parties together to drive key initiatives Ability to work within a diverse team and mentor developing team members Excellent verbal and written communication Strong team player with the ability to work within a geographically diverse team and willingness to mentor developing team members Qualifications (Requirements) Master s degree in Electrical Engineering with emphasis on Communication Engineering or Signal Processing or related field or equivalent 12+ years of experience working on systems engineering in modem design Proven experience in design and delivery of communication algorithms for the wireless PHY layer protocols such as 802.11 a/b/g/n/ac/ax/be, or cellular technologies (3G/4G/5G) or other wireless technologies Proven experience with successful tape-outs of new products Strong inter-personal skills Belief in Diversity Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.

Summary: Responsible for finding new & expanding existing accounts within IP/Chip & drive segment for PCIe/CXL and High speed ethernet testing solutions. Duties & Responsibilities: Sales Account Manager (Lab and Production) Location: Bangalore Region: India Job Description Understand R&D Lab ecosystem and test (interface, traffic and protocol) requirements. Sell into IP/ Chip and components/module ecosystem, Compute/storage (PCIe/CXL protocol testing), highspeed ethernet (DWDM transport, switching and routing traffic/ protocol testing) segments. Understand the market segments and product positioning as per customer requirements. Understands Semiconductor R&D (CPU, Accelerators/GPU, SOC, NIC, Re-timer, FPGAs, Switch ASIC etc functional groups (hardware, firmware, validation etc) and position protocol (PCIe/CXL/Ethernet/IP) testing solution. Build a next level of true partnership for engaging a customer at all levels and at earlier stages of their roadmap development. Being proactive to learn new business trends/situation i.e. PCIe Gen6.0/7.0, CXL, 1.6T ethernet, ultra ethernet, Si photonics etc within AI compute, storage drives and networking industry. Responsible for preparing quotations and updating Viavi s internal sales forecasting tools. Pre-requisites and Skills: Understanding of core underlying technologies including PCIe/CXL and Ethernet/IP. Understand technologies primarily in 3 areas photonics, Transport networks and Switching/Routing. Understanding of the whole technology ecosystem related to photonics, materials, ICs, modules, IP/Software, NEMs, production & CMs, service providers & ICP accounts. Engineering/FAE background in above mentioned technologies would be a great plus. Willing to travel to US/EMEA 2-3 times a year for training, BU engagement, tradeshows. Good English skills spoken and written. Good team player able to build consensus yet able to work remotely under minimal direct oversight. Ability to map the eco-system and fearless with cold calling and go getter. Advanced Competencies: Value Based Selling Capability while offering Business Cases/ Use Cases Able to build trust from all Customers and Viavi internal teams for having long term business as successful ones. Qualifications : Minimum 3 years of experience related to sales. BE, B-tech and/or engineering-related degree with Electronics & Communication/ Telecommunications as Major subject. MBA in Sales & Marketing is an added plus. Pre-Requisites / Skills / Experience Requirements:

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: ob Description Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 5-8 years of work experience in ASIC IP cores design RequiredBachelor's, Electrical Engineering PreferredMaster's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB/PCIE/Ethernet preferred. Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Strong experience in micro architecting RTL design from high level design specification. Excellent problem solving skills, strong communication and team work skills are mandatory. Self-driven, needs to work with minimum supervision. Experience in System Verilog, Verilog, C/C++, Perl and Python is a plus Ability to lead a small design team. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 5+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates features and functionality into hardware designs in line with proposals or roadmaps. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.