561 Asic Jobs - Page 5

Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge

About Marvell . Your Team, Your Impact The team is responsible for the post-silicon validation of high-speed transceiver ASICs for coherent optical communications within Marvell s Coherent DSP Business Unit. The team develops software validation platforms, performs post-silicon validation of hardware and firmware components of the ASIC, develops and documents user interfaces for customers, and provides technical support to Marketing, Applications, and customers. What You Can Expect Experience with End-to-End (E2E) system-level testing for wireless or networking products. Strong knowledge of FrontHaul technologies, including Radio over Ethernet (RoE), CPRI, and RFOE protocols. Understanding of Uplink and Downlink channel concepts, and general air interface concepts used in wireless communication systems. Familiar with Jenkins, GitLab CI/CD, or similar automated test frameworks and continuous integration setups. Familiarity with log analysis tools, packet capture (Wireshark), and debugging using console logs and system traces. Ability to collaborate effectively with cross-functional teams including Development, Systems, and Customer Support teams. What Were Looking For Bachelor s/ Masters degree in Computer Science, Electrical Engineering, or related fields and 2-6 years of related professional experience. Hands-on experience in Software Quality Assurance (SQA), System-Level Testing, Unit Testing, and End-to-End (E2E) Test Execution. Ability to conceptualize/implement stability & capacity/performance tests for L1. Must have prior experience in pre & post silicon validation, preferably a Wireless 5G NR / LTE / 3G, SoC - either on UE or eNB/gNB Strong understanding of wireless technologies, including 4G LTE and 5G NR protocols and testing procedures. Proficiency in Python and Shell scripting for automation, debugging, and tool development. Familiarity with Linux/Unix operating systems, including command-line utilities, basic administration, and scripting. Good problem-solving skills and ability to perform root-cause analysis on failures. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1

Support DFT on multiple types of projects in multiple design centers and apply innovative DFT techniques and affect the content of forthcoming CPU, GPU, ML and systems IP, SOCs some years before they appear in mainstream products. This candidate will contribute to DFT methodology by crafting flows, evaluating tool capabilities, helping other specialists on projects, detailing work through documentation, working with EDA vendors and propagating DFT methodologies. This position may also include meeting with customers for DFT training or to address DFT concerns. The candidate will be the first recruit in the DFT methodology group in Bangalore and will be responsible for leading the team in bangalore. Required Skills And Experience: This role is for a Principal DFT engineer with 15 years plus experience Technical leadership in DFT and ability to train/work with junior team members Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills are considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations. Experience with Siemens, Cadence and/or Synopsys DFT tools Qualified candidates will have a university degree (or equivalent) in Electronic Engineering, Computer Engineering, or other relevant technical subject area. Nice To Have Skills and Experience : Familiarity with IEEE standards such as 1500, 1149.1, 1687 and 1838 Familiarity with supporting silicon into volume production Knowledge of SSN and 3DIC Gained some exposure to digital ASIC frontend and backend design verification processes Hands-on Synthesis and Static Timing Analysis (STA) experience Familiarity with SOC architectures (Auto/Infrastructure/Client) and low power design practices would be an advantage Understanding of Functional Safety as it applies to DFT Working knowledge of Siemens MBIST and LBIST tools Exposure to simulation and formal verification tools Exposure to AI tools for execution Exposure Arm MBIST interface In Return You will be provided with the training and environment to succeed in this role. As we'll as a friendly and high-performance working environment, Arm offers a competitive benefits package including private medical insurance, sabbatical, supplementary pension, and we'llness benefits. We are offering a hybrid approach to home and office working to provide an adaptable experience for all employees and to promote a strong collaborative environment.

AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Windows, Linux and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Responsibilities & Skills Lattice is seeking candidates for the position of Senior Staff Software Development Engineer. This is a full-time position located in Pune, India. Accountabilities: Develop and deliver state-of-art database and software infrastructure for world-class ease-of-use FPGA software tool for small, mid-range and large FPGA products. Develop software capabilities for next generation of FPGA products. Support and maintain existing FPGA design tools. Contribute to Spec and Plan process - review marketing requirement documents, generate functional specifications and developer unit test plans to ensure quality software. Improve development methodologies and processes. Qualifications: BS/MS/PhD Electrical Engineering or Computer Science 12+ years of experience in large-scale software development for engineering application domains preferably in FPGA/ASIC EDA domains. Must be proficient with C++. Modern C++ proficiency is a plus. Strong background in object-oriented programming, data structures and algorithms, and graph theory Experience of working on multiple platforms - at least Linux and Windows - is required. Knowledge of shell, TCL or Python scripting is a plus. Familiarity with commercial FPGA software tools and design flow is a plus. Knowledge in FPGA logic design is a plus. Must be detail oriented and possess independent problem-solving skills. Must be able to drive projects and lead a discussion. Strong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

. Job title: Software Engineer Sr Staff - P latforms/System software development Experience: 10+ Years At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Role Responsibilities: Responsibilities for this role will involve a complete life cycle of product development spanning, (but not limited to) the following: You will be required to work with cross-functional teams to develop detailed software functional specifications, articulate system/software architecture specifications, for product features, to meet product requirements. SW development in the areas of platform infrastructure, device drivers, kernel, chassis control, device management, link, and interface management. You will be required to carry out detailed design and implementation, unit testing, integration of packet forwarding, related device/kernel drivers, and other related software components for products and features. Work closely with system and solution test teams to ensure correct and complete verification of software and components, for the feature to meet real-life network deployments. You will be required to work closely with Juniper Technical Assistance Team, for providing engineering assistance in supporting critical customer escalations for customer deployments. Requirements: Bachelor s or Master s degree in Computer Science or a related field, with 10+ years of experience in platforms/system software development. Strong technical, analytical, and problem-solving skills. Proficiency in C, C++, embedded systems, and Linux kernel/driver development. Experience working close to hardware, including device drivers, system bring-up, and Linux/OS fundamentals. Expertise in troubleshooting and debugging complex issues. Knowledge and experience with firmware, optics, SPI, retimers, FPGA, CPLD, MDIO, Ethernet interfaces (10GE - 400GE), timing protocols (SyncE, PTP), SerDes, fabric management, and chassis management are preferred. Understanding of system hardware, including buses, hardware queues/FIFOs, interrupts, BIOS, PCIe, I2C, etc., is a plus. Experience with new hardware and/or ASIC bring-up. Experience designing fault-tolerant and resilient systems is highly desirable. Excellent debugging skills and experience with various software, hardware, and memory debugging tools. Strong communication and documentation skills to articulate technical details effectively. Quick learner, self-driven, and a team player.

Leading a small team of electronics engineers Design and development of electronic sensors for automotive applications (e.g., speed sensors, pedal modules, position sensors, ABS sensors) Evaluate customer requirements and align designs with electrical functionality standards Understand and compile overseas designs, comparing customer requirements with design specifications Review and optimize electronic schematics and PCB designs for cost and time efficiency Create and validate product specifications, including electrical requirements and EMC/EMI test plans based on CISPR, ISO IEC, and OEM standards Interface with process engineering teams to resolve PCB panel design issues and ensure manufacturability Resolve technical issues related to PCB design and support both design and manufacturing teams with solutions Oversee DFMEA, prototype build documentation (BOM, process flow, testing parameters, etc.), and ensure compliance with quality standards Conduct calculations, analysis, and evaluations to ensure a high-quality and robust circuit design Provide primary technical component/module information to support cost estimation and quotation processes Support standardization efforts by referencing engineering specifications and improving the quality of existing standards Collaborate with cross-functional teams (mechanical, electrical, and process engineering) to meet design and packaging requirements Coordinate with test labs for EMC/EMI testing and documentation Lead task tracking, planning, and delegation within the project team Requirements Education: Bachelor s or higher degree in Electronics Engineering or a related field (Masters preferred) Experience: 8+ years of relevant experience in automotive process and product development Experience in leading a team Experience in the field of circuit design, sensor technology Hands-on experience in PCB population, testing, debugging, and fabrication processes Knowledge: Expertise in hardware PCB design for automotive sensors, including design flows from library creation to Gerber release Comprehensive understanding of EMI/EMC standards (CISPR, ISO IEC, IPC, MIL) and optimization techniques for automotive applications Strong knowledge of automotive sensing technologies (e.g. Hall, inductive sensing) and switches (especially two wheeler) Knowledge of FTA analysis and FIT rate Skills: Proficiency in ASIC programming, analog/digital circuit design, and tools like Altium Designer, LTSpice, and CST Studio Suite Experience in multi-layer PCB design for automotive environment and signal integrity optimization Strong skills in documentation and BOM creation Advanced computer skills in MS Office and SAP Strong English communication skills, knowledge of German or Japanese is a plus Attributes: Outgoing, adaptable, and collaborative Proactive and detail-oriented, with a commitment to delivering high-quality solutions Willingness to travel domestically and internationally

Dear Candidate Greetings for the day i am hiring for vlsi Design Engineer PAN India Location, revert with below details on swati@thinkpeople.in TOtal Exp Rel Exp: PD / DV / AMS / DFT / ASIC OR RTL Design only : Current CTC Exp CTC Location Notice Period Current Org 1.Profiles to be shared 8+ yrs onLY 2. Skills : PD / DV / AMS / DFT / ASIC OR RTL Design only only

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Description: Job Title : Digital Flow Solutions Engineer Work location : Bangalore Position requires: Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem-solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar with EDA tool operation, setup and debug: Digital: Genus, Innovus, Tempus, Voltus, etc Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent Regards Madhu/- We re doing work that matters. Help us solve what others can t.

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of a team working on the design of state of the art memory sub-system components used in their industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is seeking Senior Platform Solutions Engineer for system level bringup, debug and validation of GPU and SoC product platforms. The sophisticated nature of various chip features poses many exciting debugging situations. Someone with solid understanding and innovative thinking is required for on time release of the products. As part of the Silicon Solutions Team, we are responsible for productizing NVIDIAs chips into groundbreaking consumer, professional, server, mobile, and automotive solutions. What you will be doing: Silicon and board bring up, validation, and debug from prototype to production. Responsible for the GPU and SoC system qualification including feature checks, system stress at PVT conditions, enablement and debug of product platforms at module or tray level. Communicate with team members contributing to PCB design, PCB architecture, system architecture, PCB Layout, Mechanical, Thermal, Chip Arch and product management for effective platform validation Debug complex ASIC and PCB issues related to logic design, signal integrity and power delivery in a high energy work environment, with a team that is the best in the business! Understand architecture of next generation chips and platforms, develop test plans, scripts and implement. Understand various HW features related to system power, performance and thermal. Develop new methodologies to improve the silicon validation process and take it to the next level! What we need to see: BTech/BE or MTech/ME degree in Electronics with 5+ years of work experience. Good knowledge in board and system design considerations, experience in silicon design/bring up. Platform design experience with exposure to datacenter hardware architecture and product development Strong understanding of system components like CPU, GPU, Networking, BMC and other connected peripherals Understanding of x86, ARM and GPU system architecture for server design Very good problem solving and debugging skills. Must be a standout colleague and ready to work with global teams from diverse cultural backgrounds. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

Support Global Projects by adapting HVDC Base Control & Protection Software (MACH). Develop Control and Protection Functions / Solutions for future HVDC technologies. Perform Power system protection / control studies using EMT tool based on p roject requirement s to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Coordinate with different stakeholders across the business units to get inputs to optimize the HVDC solutions. Living Hitachi Energy s core values of safety and integrity, which means taking responsibility for your own actions while caring for your colleagues and the business. Your background: Bachelor s degree in electrical and Electronics w ith a minimum work experience of 2 to 5 years in Control and Protection system . You should have knowledge in PSCAD, MATLAB, or any other Simulation Software . You must have b asic knowledge on IEEE / IEC standards . You should have experience in substation environment and protection application. Experience in technical tender support or bidding is preferrable. Experience in substation environment and protection application is an added advantage. Self-starter caliber who could own tasks through to completion. Excellent written and verbal communication skills. .

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, data center, and networking applications. What You Can Expect As a Senior Staff Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 9+ years of experience running an industry standard EDA tool for PnR & signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar with EDA tool operation, setup and debug: Digital: Genus, Innovus, Tempus, Voltus, etc We re doing work that matters. Help us solve what others can t.

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

SENIOR SILICON DESIGN ENGINEER ASIC Physical Design Engineer THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Provide technical support to other teams PREFERRED EXPERIENCE: 5years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SMTS SILICON DESIGN ENGINEER (AECG ASIC Physical Design Implementation) THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 14years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 10years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

CPU Performance Validation Engineer THE ROLE: The person will be part of AMDs CPU Performance Validation team. This team is part of AMDs global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It s always We before Me in the team KEY RESPONSIBILITIES: Responsible for building infrastructure for performance verification and verify performance of X86 processor. Writing specific targeted tests to measure the performance of the processor Involves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for CORE or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation PREFERRED EXPERIENCE: Experience: 2-5 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevant research and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work LOCATION: Bangalore #LI-Hybrid #LI-RR1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV Benefits offered are described: AMD benefits at a glance .

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do: Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. Manage project-specific ASIC development flow setup and maintenance. Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities. Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database. Ensure correct IP and pad-ring integration in block and flat designs. Mentor junior PD/PV team members and oversee their tasks. You will be reporting to ASIC Design Director. What Youll Need: Minimum 12+ Years of experience in ASIC/ SoC Physical Design. Skills - have working experience in advanced FinFET node designs. Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must. Education - B. Tech /M. Tech in Electronics Engineering. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

About Tessolve Tessolve is a leading engineering solutions provider, enabling silicon and system companies to accelerate their products to market. With capabilities across silicon design, test engineering, and embedded solutions, we are an end-to-end partner for semiconductor companies globally. Job Description We are looking for a Senior STA Engineer with 8 10 years of hands-on experience in Static Timing Analysis for complex SoC/ASIC designs at advanced technology nodes (7nm, 5nm, or below). The ideal candidate should be technically sound, self-driven, and capable of independently owning STA tasks from RTL to signoff. Key Responsibilities Perform full-chip and block-level static timing analysis using tools such as Primetime , Tempus , or equivalent. Develop and validate timing constraints (SDC) for functional and DFT modes. Drive timing closure in collaboration with physical design, synthesis, and DFT teams. Analyze and resolve setup/hold, transition time, and cross-corner violations. Perform timing ECOs and timing model generation for hierarchical designs. Support signoff flows, including OCV, AOCV, POCV , and SI/IR-drop aware timing. Script automation in TCL/Perl/Python to improve STA efficiency. Participate in customer calls and support project execution in a global delivery model. Required Skills Strong fundamentals in STA, CMOS timing, and VLSI design concepts. Expertise in timing constraints, derating, and ECO implementation. Experience in hierarchical and flat STA at chip-level. Hands-on with timing sign-off methodologies across multiple PVT corners. Familiarity with clock domain crossing (CDC) and false path/multicycle path analysis. Working knowledge of physical design flows is a plus. Good communication and leadership skills. Educational Qualifications B.E/B.Tech or M.E/M.Tech in Electronics or related discipline. Nice to Have Experience with advanced technology nodes (5nm/3nm) . Familiarity with low-power design techniques (UPF) . Customer interaction and project leadership experience.

DIRECTOR OF MARKETING www.einfochips.com Job Description, Role Responsibilities POSITION TITLE: Engineer / Sr Engineer (Linux BSP) EXPERIENCE: 4-10 Years Role: Linux BSP LOCATION: Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore Company Profile eInfochips An Arrow Company (www.einfochips.com) is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company s service offerings include digital transformation and connected IoT solutions, Including IoT Security, across various cloud platforms, including AWS and Azure. Our work culture is built over years of experience in providing innovative solutions to our clients and our indomitable spirit to excel in all aspects of our engagement. We believe that our success lies upon the skills and quality of our people we work with. Silicon engineering services: ASIC / FPGA Design Development, Design Verification Validation, Physical Design DFT Embedded systems engineering services: Hardware Design, System Software, System Verification Validation, Multimedia Software engineering services: Cloud Enablement, IoT Mobility, Application Software, QA and Test Automation, BI and Data Visualization Extended services: New Product Development, Lifecycle Management, Product Sustenance IPs: DevOps for IoT, IoT Gateway Framework, IoT Device Lifecycle Management, Video Management Software, Reusable Camera Framework, Test Automation Framework, Reference Designs EVMs, Verification IPs, OptiX Physical Design Framework About Arrow Electronics Arrow Electronics (www.arrow.com) guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2021 sales of $34.48 billion, we develop technology solutions that improve business and daily life. Our strategic direction of guiding innovation forward is expressed as Five Years Out (Five Years Out | Arrow Electronics), a way of thinking about the tangible future to bridge the gap between what s possible and the practical technologies to make it happen. http://www.einfochips.com/ http://www.einfochips.com/ https: / / www.arrow.com / company / fiveyearsout / https: / / www.arrow.com / company / fiveyearsout / www.einfochips.com Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results- oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies. In addition, the right candidate will: Incumbent works under general supervision Incumbent has substantial experience to resolve problems and concepts Incumbent can work on complex concepts and implementation http://www.einfochips.com/ www.einfochips.com Be a highly energetic self-starter Be an open and excellent communicator Have exceptional interpersonal skills Be a consummate team player Interface well with Client Engineer Team members and other Business Units of eInfochips Finally, this individual must have an uncompromising level of personal integrity. Education A Graduate degree in Electronics and communication/Information Technology/Computer-Science is required. A Masters technical degree is highly desirable. Do you want to know more about usKindly click any of the following links based on your interest. Our Website: Click here Our Corporate Video: Click here Our Leadership Team: Click here Our Linkedin profile: Click here Our CSR Initiatives: Click here Our Life @ eInfochips: Click here Our Industry Recognition Awards: Click here Our Youtube archive: Click here OUR CORE VALUES a. Customer First b. Disciplined Execution c. Embrace Impossible Challenges d. Continous Learning e. . Product Services Company

THE ROLE: The Core design team is responsible for development of High performance and Ultralow power x86 microprocessor core . The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients / server) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. KEY RESPONSIBILITIES: RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Design of x86 Core microarchitecture features, power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Micro-architecting and documentation of the design features Mentor the junior members of the RTL team to meet the team goals Your commitment to innovating as a team member demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: 11+ years of experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow is an added plus. Ability to program with scripting languages such as Python or Perl is a plus; Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: Master s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance .