561 Asic Jobs - Page 7

MTS SOFTWARE DEVELOPMENT ENG INEER THE ROLE: AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: 7 years and Above years of total experience and Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Linux,RTOS and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent #LI-SK4 Benefits offered are described: AMD benefits at a glance .

Engineer / Sr Engineer (Linux BSP), eInfochips, 4 - 10 years, Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore - ACHNET Are you sure you want to cancel? Are you sure you want to cancel this Profile? You can always come back later Edit Profile The first thing people see You do not have permission to access the Talent Management menu. This section is restricted to Admins and Editors only. If you believe you should have access, please contact your administrator for assistance. YOUR BROWSER IS NOT SUPPORTED To view this experience, please upgade to the latest one of these browsers Engineer / Sr Engineer (Linux Bsp) DESCRIPTION Job Description, Role Responsibilities POSITION TITLE: EXPERIENCE: Role: LOCATION: Engineer / Sr Engineer (Linux BSP) 4-10 Years Linux BSP Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore Company Profile eInfochips An Arrow Company (www.einfochips.com) is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company s service offerings include digital transformation and connected IoT solutions, Including IoT Security, across various cloud platforms, including AWS and Azure. Our work culture is built over years of experience in providing innovative solutions to our clients and our indomitable spirit to excel in all aspects of our engagement. We believe that our success lies upon the skills and quality of our people we work with. Silicon engineering services: ASIC / FPGA Design Development, Design Verification Validation, Physical Design DFT Embedded systems engineering services: Hardware Design, System Software, System Verification Validation, Multimedia Software engineering services: Cloud Enablement, IoT Mobility, Application Software, QA and Test Automation, BI and Data Visualization Extended services: New Product Development, Lifecycle Management, Product Sustenance IPs: DevOps for IoT, IoT Gateway Framework, IoT Device Lifecycle Management, Video Management Software, Reusable Camera Framework, Test Automation Framework, Reference Designs EVMs, Verification IPs, OptiX Physical Design Framework About Arrow Electronics Arrow Electronics (www.arrow.com) guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2021 sales of $34.48 billion, we develop technology solutions that improve business and daily life. Our strategic direction of guiding innovation forward is expressed as Five Years Out (Five Years Out | Arrow Electronics), a way of thinking about the tangible future to bridge the gap between what s possible and the practical technologies to make it happen. www.einfochips.com Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies. In addition, the right candidate will: Incumbent works under general supervision Incumbent has substantial experience to resolve problems and concepts Incumbent can work on complex concepts and implementation www.einfochips.com Be a highly energetic self-starter Be an open and excellent communicator Have exceptional interpersonal skills Be a consummate team player Interface well with Client Engineer Team members and other Business Units of eInfochips Finally, this individual must have an uncompromising level of personal integrity. Education A Graduate degree in Electronics and communication/Information Technology/Computer-Science is required. A Masters technical degree is highly desirable.

Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results- oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies.

The opportunity: Hitachi Energy is a world leader that is advancing a sustainable energy future for all. We are advancing the world s energy system to be more sustainable, flexible, and secure, and we collaborate with customers and partners to enable a sustainable energy future - for today s generations and those to come. The Hitachi Energy Indian Operations Center (INOPC) is a competence center with around 3000+ skilled engineers who focus on tendering, engineering, planning, procurement, project Management, functional system testing, installation supervision, documentation and commissioning. However, over the last decade, it has evolved to become the largest Operations hub. The India Operations Centre team at Chennai, Bangalore and Gurugram supports Hitachi Energy s units in more than 40 countries across a wide portfolio of all the four business units in Hitachi Energy To date, the team has executed engineering and commissioning for projects in more than 80 countries. The technical marketing engineer for Mission Critical telecommunication Solutions (MCS) has the global responsibility to enable the Pre-Sales Sales community of the different regional HUBs to understand technical market requirements for wired telecommunication networks and ensure customer interaction in line with global solution/product strategy. Support sales organizations in driving sales by your technical expertise . Provide relevant customer market inputs to product management and RD activities, ensuring market alignment and relevance . How you ll make an impact: Design HVDC Protection Logics and Algorithms for HVDC Protects across the globe. Develop Protection Functions / Solutions for HVDC Project. Perform Power system protection coordination based on Project requirement to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Design HVDC Protection Logics and Algorithms for HVDC Protects across the globe. Develop Protection Functions / Solutions for HVDC Project. Perform Power system protection coordination based on Project requirement to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Coordinate with different stakeholders across the business units to get inputs to optimize the HVDC solutions. Living Hitachi Energy s core values of safety and integrity, which means taking responsibility for your own actions while caring for your colleagues and the business. Your background: Bachelor s degree in electrical and Electronics w ith a minimum work experience of 6+ years in Control and Protection system . You should have knowledge in PSCAD, MATLAB, or any other Simulation Software . You must have b asic knowledge on IEEE / IEC standards . You should have experience in substation environment and protection application. Experience in technical tender support or bidding is preferrable. Experience in substation environment and protection application is an added advantage. Self-starter caliber who could own tasks through to completion. Excellent written and verbal communication skills. Qualified individuals with a disability may request a reasonable accommodation if you are unable or limited in your ability to use or access the Hitachi Energy career site as a result of your disability. You may request reasonable accommodations by completing a general inquiry form on our website. Please include your contact information and specific details about your required accommodation to support you during the job application process. .

Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) Job Description ASIC Verification Lead Summary of the offer: Integrating ASIC functional verification team. ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers). Using Constraint-Random, Coverage Driven functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. Main responsibilities: Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams. Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications. Write and perform closely test plans with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog / C ++ Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Submit recommendations on tools and methodologies to develop to improve productivity. Mentor junior engineers on how to produce a maintainable and reusable code across projects. Skills: Participated in the successful verification of a complex SoC or ASIC. Mastering UVM or equivalent verification methodology. Proficient developer of Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA) Strong knowledge of simulation tools and coverage database visualization tools Developed test plans that helped identifying sharp functional defects. efficiency in problem solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints Experienced in improving processes and methodologies Experience in managing tasks for a small team. Required minimum experience: 7 years Required minimum studies: Master/Engineer in Electronics and Communication Engineering.

About the Role: 07 Job Description Department overview: As a global leader in trade and transaction reporting, the S&P Cappitech team have been providing RegTech solutions for over two decades. Our cloud-based, cross regulation SaaS platform allows banks, brokers, hedge funds, asset managers, insurance companies and corporates to comply with global regulatory requirements. Our support team is expanding, and you will play an important role in continuing to make it all happen. You will be joining a team of problem solvers and solution finders with a passion for providing the very best customer experience in a fast-paced environment. We are a diverse team supporting our global customers. S&P values focus on inclusiveness, collaboration and integrity and our management strive to provide a work environment that encourages our colleagues to achieve their full potential. Position summary We are looking for a someone who can provide exceptional customer experience to a broad range of clients and ensure the fast and effective management of client workflows to join the S&P Cappitech Support and Operations team. The ideal candidate will be comfortable in communicating with clients, answering regulatory queries, and resolving daily reporting issues. Ideally the candidate will have some understand in EMIR, MiFID, ASIC, CFTC, SEC andor SFTR. The role is client facing and requires a high degree of technical competence. Duties and accountabilities Dealing with customer enquiries and requests and managing them efficiently and in a timely manner until resolution Helping clients understand how the solution works and how to resolve reporting issues Involvement in client training and site visits Escalate issues in a timely manner and ensure follow and resolution. Assist in validation or UAT for issue resolution Working on Client specific projects Business competencies Experience Client facing experience Financial services experience preferred particularly securities and derivatives finance Knowledge of transaction reporting desired Ability to grasp concepts of a technical nature Advanced MS Excel skills preferred Understanding of SQL, API preferred Knowledge of other vendor systems useful - PostTrade systems, Core Banking Systems, etc. Personal competencies Personal impact Strong analytical skills Be proactive and able to work independently Ability to listen, learn quickly and demonstrate initiative Good attention to detail Focused on delivery Communication Must be an excellent written and verbal communicator Excellent interpersonal skills Able to easily adapt communication style in different situations Committed to high quality output Highly motivated, disciplined, confident and a team player. The ability to adjust to shifting priorities is a must Ability to collaborate effectively with team Additional languages a plus, especially Spanish, Japanese What's In It For You Our Purpose: Progress is not a self-starter. It requires a catalyst to be set in motion. Information, imagination, people, technology-the right combination can unlock possibility and change the world. Our world is in transition and getting more complex by the day. We push past expected observations and seek out new levels of understanding so that we can help companies, governments and individuals make an impact on tomorrow. At S&P Global we transform data into Essential Intelligence, pinpointing risks and opening possibilities. We Accelerate Progress. Our People: We're more than 35,000 strong worldwide-so we're able to understand nuances while having a broad perspective. Our team is driven by curiosity and a shared belief that Essential Intelligence can help build a more prosperous future for us all. From finding new ways to measure sustainability to analyzing energy transition across the supply chain to building workflow solutions that make it easy to tap into insight and apply it. We are changing the way people see things and empowering them to make an impact on the world we live in. We're committed to a more equitable future and to helping our customers find new, sustainable ways of doing business. We're constantly seeking new solutions that have progress in mind. Join us and help create the critical insights that truly make a difference. Our Values: Integrity, Discovery, Partnership At S&P Global, we focus on Powering Global Markets. Throughout our history, the world's leading organizations have relied on us for the Essential Intelligence they need to make confident decisions about the road ahead. We start with a foundation of integrity in all we do, bring a spirit of discovery to our work, and collaborate in close partnership with each other and our customers to achieve shared goals. Benefits: We take care of you, so you can take care of business. We care about our people. That's why we provide everything you-and your career-need to thrive at S&P Global. Our benefits include: Health & Wellness: Health care coverage designed for the mind and body. Flexible Downtime: Generous time off helps keep you energized for your time on. Continuous Learning: Access a wealth of resources to grow your career and learn valuable new skills. Invest in Your Future: Secure your financial future through competitive pay, retirement planning, a continuing education program with a company-matched student loan contribution, and financial wellness programs. Family Friendly Perks: It's not just about you. S&P Global has perks for your partners and little ones, too, with some best-in class benefits for families. Beyond the Basics: From retail discounts to referral incentive awards-small perks can make a big difference. For more information on benefits by country visit: Global Hiring and Opportunity at S&P Global: At S&P Global, we are committed to fostering a connected and engaged workplace where all individuals have access to opportunities based on their skills, experience, and contributions. Our hiring practices emphasize fairness, transparency, and merit, ensuring that we attract and retain top talent. By valuing different perspectives and promoting a culture of respect and collaboration, we drive innovation and power global markets. ----------------------------------------------------------- Equal Opportunity Employer S&P Global is an equal opportunity employer and all qualified candidates will receive consideration for employment without regard to race/ethnicity, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, marital status, military veteran status, unemployment status, or any other status protected by law. Only electronic job submissions will be considered for employment. If you need an accommodation during the application process due to a disability, please send an email to: and your request will be forwarded to the appropriate person. US Candidates Only: The EEO is the Law Poster describes discrimination protections under federal law. Pay Transparency Nondiscrimination Provision - ----------------------------------------------------------- 20 - Professional (EEO-2 Job Categories-United States of America), OPRTON203 - Entry Professional (EEO Job Group)

Role & responsibilities - Support team in requirements gathering Assisting in dividing the task into domain Co-ordinating with cross functional team to collate the data To extensively do the research on the requirement from customer Support team in specification creation. Assisting in development activities and documentation Key skills and expectations Strong fundamentals in electrical and electronic devices and circuits. Strong fundamentals in communication theories and concepts. Strong fundamentals in Microprocessor, Microcontroller and programmable devices. Strong fundamentals in wireless design concepts like RF, microwave. Exposure to the VLSI design like FPGA and ASIC is highly recommended. Willingness and ability to learn and adapt to cutting-edge technologies. Good software programming skills. Good communication skills and interpersonal skills. Good performance in academics. Good in documentation using Microsoft office tools.

Summary Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre) and India (Bangalore), EnSilica currently employs more than 160 people. We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica. You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective and pragmatic verification strategy and gain the support of the end-customer for the chosen approach. You will need to understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process. Responsibilities Verification specialist working on customer and internal projects often as the verification lead. Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods. You would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment. Active participation in the verification community to drive the introduction of new and effective techniques within our business to help solve the verification challenges faced by our customers. Close working with our customers to build a strong relationship that results in repeat business. Education / Key Skills / Experience BE/ME in Electronics /Computer Science 1 group University. 15+ years experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and SystemVerilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Strong VHDL/Verilog RTL. Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standards compliances will be considered as a strong plus Personality Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated achiever who gains satisfaction from providing excellent customer service and has a can-do attitude. Happy to take ownership of problems and provide suitable solutions. Creative problem solving. Team player. Ability to work in a dynamic environment.

Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) Verificaiton Engineer Integrating ASIC functional verification team. ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers). Using Constraint-Random, Coverage Driven functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. Main responsibilities: Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain and publish the verification specification. Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects. Skills and capacities: Curious, demanding and rigorous. Mastering object oriented programming. Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA) Knowledge of simulation tools and coverage database visualization tools Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi is expanding its team in Chiplet Architecture and Design! We are looking for experienced RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and engage in the complete ASIC development cycle, from concept to product. We are seeking a seasoned SoC leads to work with a team to solve complex problems while optimizing performance, area, and power on leading-edge SoC systems. This team helps build new and innovative connectivity products tailored to world changing solutions for AI accelerators, Compute, IO, and Memory Chiplets. What Youll Do: You will manage the design / RTL team to achieve the project goals You will work with customer, provide technical support and provide collaterals agreed upon. You will work with team to achieve flow, methodology improvements to achieve high reuse. You will work with IP vendors to generate / get right configurations of the IP. You will manage teamwork allocation, schedule, risk mitigation and deliverables from design team. Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for the SOC. Interact with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). Work with the cross-functional team of verification, DFT, Physical Design, emulation, and software teams to make design decisions and represent Design status throughout the development process. What youll have: Education: Bachelors or masters degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 15+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 15+years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication & Leadership: Strong leadership and communication skills to ensure effective program execution. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

Roles and Responsibility PD: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM) Well versed with the timing closure (STA), timing closure methodologies Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification Experience in lower tech node ( Good automation skills in PERL, TCL and EDA tool-specific scripting Able to take complete ownership for Block/sub-system for complete execution cycle Out of box thinking to meet tighter PPA requirements Qualification: BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired Experience - 11+

Apply to this job Meta is seeking a highly skilled and experienced ASIC Systems Engineer to join our team. As a key member of our engineering team, you will be responsible for designing, developing, and maintaining Linux device drivers/kernel modules, user-space drivers, user-space libraries and APIs, system services and daemons, performance optimization/benchmarking tools, and diagnostics tools that support Metas advanced AI accelerator ASIC in production. ASIC Engineer, Accelerator Systems Responsibilities Design, develop, and maintain Linux device drivers/kernel modules, user-space drivers, user-space libraries and APIs, system services and daemons to support the ASIC Develop diagnostics tools to troubleshoot and debug issues with the ASIC and related software components Optimize and benchmark the performance of the ASIC and related software components Collaborate with hardware engineers to understand the ASIC architecture and design Collaborate with software engineers to integrate the ASIC into the overall software stack Participate in code reviews and contribute to the development of best practices Stay up-to-date with the latest developments in Linux kernel development and related technologies Minimum Qualifications BS/MS in Computer Science or a related field 12+ years of experience in Linux systems development Expertise knowledge of C and C++ programming languages Experience of developing diagnostic/telemetry tools and RAS features Experience with Linux kernel internals, device drivers, and kernel modules Experience with user-space driver development and API design Knowledge of computer architecture and hardware design principles Experience with performance optimization and benchmarking Proven problem-solving skills and able to work independently Excellent proficiency in both written and oral communication Preferred Qualifications Experience with AI accelerator ASICs Experience with continuous integration and continuous deployment (CI/CD) pipelines Experience with performance optimization and benchmarking Experience of developing RAS features for a product About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

RoleSenior CAD Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

RoleASIC CAD Lead Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a ASIC CAD Lead Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

locationsIndia, Bangalore time typeFull time posted onPosted 17 Days Ago job requisition idJR0274344 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications.Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to micro-architecture specifications.Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.Replicates, root causes, and debugs issues in the pre-silicon environment.Finds and implements corrective measures to resolve failing tests.Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.Maintains and improves existing functional verification infrastructure and methodology.Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum Qualifications:BS with 10+ years/MS with 8+ years industry experiencesExperience on Pre-Si validation on Emulation, preferably Zebu.Experience on validation at MCP.Experience with pre-Si verification with System Verilog OVM/UVM on content development Scripting languages such as Python, Simics.Good understanding of RTL, Verilog, VHDL.Preferred Qualifications:Experience with Synopsys simulation and coverage tools.Assertion based verificationRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0272648 Job Details: About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 10+ years of industry experience, OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 8+ years of industry experience The years of experience mentioned above must focus on formal verification Preferred Qualifications: Knowledge of GPU Formal verification experience in at least one of these areasArbitration logic, low power design, memory controller, transaction router/bridge. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0270512 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 5+ years of industry experience, or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 3+ years of industry experience Years of experience must include at least three of the following skills: Hardware architectures, system level IC design implementation knowledge of how to create end use scenarios IP level or SoC level validation experience Processor-based SoC level verification, in native Verilog, SystemVerilog and UVM mixed environments Verification tools such as VCS, waveform analyzer and/or third-party VIP/BFM integration (e.g. Synopsys VIPs) UVM verification Strong understanding of design concepts and ASIC flow Preferred Qualifications and experience that will make you stand out: Prior work on GDDR memory, power management, peripherals, datapath verification or PCIe Protocol is desirable Understanding of AXI-AMBA. Protocol variants is desirable Strong technical background in FPGA prototype emulation and debug Proven technical background in silicon validation, failure analysis and debug Validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART Prior hands-on automation script development and optimization using C/C++, Python Good understanding of embedded firmware/software development process Functional knowledge and experience in JTAG Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Looking for below - Architect/Lead ASIC designer/Lead Design verification/Lead Formal Verification/Lead Emulation/Lead Synthesis Engineer/Lead Implementation Engineer/Lead DFT Engineer/Lead Share your updated CV at jatin@smrd.in

As an RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout. What Youll Do: Micro architect and RTL Design of SoC SubSystem/IP blocks Will develop UPF and run CLP checks Will be responsible for RTL quality checks - Lint/CDC/LEC Create appropriate documentation for hardware blocks. Responsible for analyse / debug / fixing issues reported by verification team Will develop the synthesis constraints for the blocks / subsystem Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation What Youll Need: Education: Bachelors or masters degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 5+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 5+ years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication Leadership: Strong leadership and communication skills to ensure effective program execution.

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

The opportunity: Hitachi Energy is a world leader that is advancing a sustainable energy future for all. We are advancing the world s energy system to be more sustainable, flexible, and secure, and we collaborate with customers and partners to enable a sustainable energy future - for today s generations and those to come. The Hitachi Energy Indian Operations Center (INOPC) is a competence center with around 30 00 + skilled engineers who focus on tendering, engineering, planning, procurement, project Management, functional system testing, installation supervision, documentation and commissioning. However, over the last decade, it has evolved to become the largest Operations hub. The India Operations Centre team at Chennai, Bangalore and Gurugram supports Hitachi Energy s units in more than 40 countries across a wide portfolio of all the four business units in Hitachi Energy To date, the team has executed engineering and commissioning for projects in more than 80 countries. The technical marketing engineer for Mission Critical telecommunication Solutions (MCS) has the global responsibility to enable the Pre-Sales Sales community of the different regional HUBs to understand technical market requirements for wired telecommunication networks and ensure customer interaction in line with global solution/product strategy. Support sales organizations in driving sales by your technical expertise . Provide relevant customer market inputs to product management and RD activities, ensuring market alignment and relevance . How you ll make an impact: Design HVDC Protection Logics and Algorithms for HVDC Protects across the globe. Develop Protection Functions / Solutions for HVDC Project. Perform Power system protection coordination based on Project requirement to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Design HVDC Protection Logics and Algorithms for HVDC Protects across the globe. Develop Protection Functions / Solutions for HVDC Project. Perform Power system protection coordination based on Project requirement to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Coordinate with different stakeholders across the business units to get inputs to optimize the HVDC solutions. Living Hitachi Energy s core values of safety and integrity, which means taking responsibility for your own actions while caring for your colleagues and the business. Your background: Bachelor s degree in electrical and Electronics w ith a minimum work experience of 1 to 6 years in Control and Protection system . You should have knowledge in PSCAD, MATLAB, or any other Simulation Software . You must have b asic knowledge on IEEE / IEC standards . You should have experience in substation environment and protection application. Experience in technical tender support or bidding is preferrable. Experience in substation environment and protection application is an added advantage. Self-starter caliber who could own tasks through to completion. Excellent written and verbal communication skills. Qualified individuals with a disability may request a reasonable accommodation if you are unable or limited in your ability to use or access the Hitachi Energy career site as a result of your disability. You may request reasonable accommodations by completing a general inquiry form on our website. Please include your contact information and specific details about your required accommodation to support you during the job application process. .

The opportunity: Hitachi Energy is a world leader that is advancing a sustainable energy future for all. We are advancing the world s energy system to be more sustainable, flexible, and secure, and we collaborate with customers and partners to enable a sustainable energy future - for today s generations and those to come. The Hitachi Energy Indian Operations Center (INOPC) is a competence center with around 30 00 + skilled engineers who focus on tendering, engineering, planning, procurement, project Management, functional system testing, installation supervision, documentation and commissioning. However, over the last decade, it has evolved to become the largest Operations hub. The India Operations Centre team at Chennai, Bangalore and Gurugram supports Hitachi Energy s units in more than 40 countries across a wide portfolio of all the four business units in Hitachi Energy To date, the team has executed engineering and commissioning for projects in more than 80 countries. The technical marketing engineer for Mission Critical telecommunication Solutions (MCS) has the global responsibility to enable the Pre-Sales Sales community of the different regional HUBs to understand technical market requirements for wired telecommunication networks and ensure customer interaction in line with global solution/product strategy. Support sales organizations in driving sales by your technical expertise . Provide relevant customer market inputs to product management and RD activities, ensuring market alignment and relevance . How you ll make an impact: Support Global Projects by adapting HVDC Base Control Protection Software (MACH). Develop Control and Protection Functions / Solutions for future HVDC technologies. Perform Power system protection / control studies using EMT tool based on p roject requirement s to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Coordinate with different stakeholders across the business units to get inputs to optimize the HVDC solutions. Living Hitachi Energy s core values of safety and integrity, which means taking responsibility for your own actions while caring for your colleagues and the business. Your background: Bachelor s degree in electrical and Electronics w ith a minimum work experience of 2 to 5 years in Control and Protection system . You should have knowledge in PSCAD, MATLAB, or any other Simulation Software . You must have b asic knowledge on IEEE / IEC standards . You should have experience in substation environment and protection application. Experience in technical tender support or bidding is preferrable. Experience in substation environment and protection application is an added advantage. Self-starter caliber who could own tasks through to completion. Excellent written and verbal communication skills. Qualified individuals with a disability may request a reasonable accommodation if you are unable or limited in your ability to use or access the Hitachi Energy career site as a result of your disability. You may request reasonable accommodations by completing a general inquiry form on our website. Please include your contact information and specific details about your required accommodation to support you during the job application process. .