561 Asic Jobs - Page 6

P MTS SILICON DESIGN ENGINEER (AECG ASIC PD Architect) THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design architecture and flow development for next generation ASICs that meet Engineering, Business and Customer requirements. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Technical Physical Design lead on AECG ASIC solutions, focused on driving the best Power, Performance, Area for customers. Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase. Provide expert guidance to physical design execution teams within AMD and with external partners to drive delivery to customer commitments. Develop technical relationships with broader AMD Design/CAD community and peers. PREFERRED EXPERIENCE: Strong understanding of development of custom ASICs for external customers. Strong background in physical design with exposure to circuit and logic design. Proven track record of delivering SOCs in process technologies 7nm and below. Expert user of P&R, Timing and Physical verification tools from top EDA vendors. Proven expertise in developing physical implementation flows as required. Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design. Experience in leading a small team of high performing individuals. EDUCATION & EXPERIENCE: BS or MS degree in in Electrical Engineering or Computer Science. 16+years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

. Job Title: Software Engineer 3 Experience: 4+ Years Responsibilities for this role will involve a complete life cycle of product development spanning, (but not limited to) the following: You will be required to work with cross-functional teams to develop detailed software functional specifications, articulate system/software architecture specifications, for product features, to meet product requirements. SW development in the areas of platform infrastructure, device drivers, kernel, chassis control, device management, link, and interface management. You will be required to carry out detailed design and implementation, unit testing, integration of packet forwarding, related device/kernel drivers, and other related software components for products and features. Work closely with system and solution test teams to ensure correct and complete verification of software and components, for the feature to meet real-life network deployments. You will be required to work closely with Juniper Technical Assistance Team, for providing engineering assistance in supporting critical customer escalations for customer deployments. Requirements: Bachelors or master s in computer science or similar field with 4+ years experience in Platforms/System software development. Strong technical, analytical, and problem-solving skills are key. Strong in C, C++, Embedded Systems and Linux Kernel/Driver development Proficient in working close to hardware - device drivers, system bring-up, Linux/OS fundamentals. Proficient in troubleshooting and debugging complex issues. Good understanding and experience of firmware, Optics, SPI, Retimers, FPGA, CPLD, MDIO, Ethernet Interfaces (10ge - 400ge), timing protocols (SyncE, PTP, etc.), Serdes, Fabric anagement, Chassis management is preferable. Knowledge of how system hardware works is a plus: buses, hardware queues/FIFOs, interrupts, BIOS, PCIe, I2C, etc. Experience on bringing up new hardware and/or ASIC Experience working on paradigms to design fault-tolerant and resilient systems will be a big plus Excellent debugging skills and rich experience using various software, hardware, memory debugging tools Ability to articulate technical details via good communication and documentation skills. Quick learner, self-driven, and a team player. Wherever you are in the world, whether its downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their lifes work. At Juniper we believe this is more than a job - its an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We d love to speak with you. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need.

. Job Title: Software Engineer 4 - Broadcom PFE Experience: 7+ Years About ACX Platform Software Team ACX platform is part of WAN BU, Our team in Juniper is responsible for driving technology leadership in the Juniper routing, access, and aggregation router developments for next-generation Metro and 5G networks, deployed in some of the world s largest service providers, data centers, enterprise, and metro ethernet networks. We are driving Juniper s growth in revenue and market share in service provider, data center, enterprise, access, and aggregation space, by delivering market-leading products with continuous innovation and relentless execution. These products (either modular or chassis-based) are based on either Juniper homegrown switching ASIC or based on merchant silicon. JOB DESCRIPTION We are looking for authoritative engineers for the Access & Aggregation product s PFE team. Work encompasses crafting, designing and developing forwarding software for merchant ASIC-based Platforms. You will get an opportunity to develop features in CFM, BFD, TWAMP, RFC2544, Y.1564 on Broadcom Qumran, Jericho ASICs What are our requirements? We are in search of someone who has good knowledge of Router/Switch architecture. Your prior work experience in any one of the domains is helpful CFM, LFM, Y.1731, Y.1564, RFC2544, BFD, TWAMP, LACP, Multi Chassis LAG, VPLS, EVPN MPLS, Experience/knowledge of Unix/Linux kernel Understanding of system architecture for network processor based products Experience in design/development of forwarding software Prior experience with Broadcom ASICS like Qumran/Jericho is helpful Your experience in trouble-shooting problems in actual customer network deployments or in complex lab topologies will be helpful. Do you have strong Coding and debugging skills with extensive experience in core file analysis? We are hiring someone with 6+ years of experience, preferably in a router/switch company. A deep understanding of concepts related to computer architecture, data structures and programming practices is desirable. A Bachelor/Masters Degree in Electrical Engineering or Computer Science.

[BLR] Network Infrastructure Software Development Technical Lead Bengaluru, India About Arrcus Arrcus was founded to enhance business efficiency through superior network connectivity. The Arrcus Connected Edge (ACE) platform offers best-in-class networking with the most flexible consumption model at the lowest total cost of ownership. The Arrcus team consists of world-class technologists who have an unparalleled record in shipping industry-leading networking products, complemented by industry thought leaders, operating executives, strategic partners, and top-tier VCs. The company is headquartered in San Jose, California. For more information, go to www.arrcus.com or follow @arrcusinc . We offer a variety of roles in software, hardware, and cloud environments. We are looking for people who are self-motivated, creative, and agile. You will work closely with the top-notch talent in Arrcus in redefining networking. Responsibilities Bring-up networking ASICs and platforms. Write Feature Spec covering the requirements and detailed design Implement improvements and features individually or as part of a team Triage, resolve internal and customer found issues Evaluate, Integrate third party libraries Peer review of Feature Spec, Code, Test Plan and other engineering documents Improve performance/scale of existing features/solutions Help with interview, onboarding and mentoring of new hires Work with customer and product teams to understand new requirements Plan, schedule, track and periodically report the project status all the way to customer delivery Education/Qualifications BS/MS/PhD in Computer Engineering/Computer Science or equivalent degree Ability to write high-quality C/C++/Go/Python code 8+ years of relevant hands-on development experience in some of the following technologies Linux OS internals, Kernel, memory management and network stack Debian Build, Packaging, Install, Upgrade frameworks Networking - TCP/IP, Routing Messaging systems and datastores such as etcd, consul, Redis High Availability and ISSU Containers, Virtual Machines (VM). Orchestration frameworks like Kubernetes, KVM. Prior work experience in a startup or venture-backed company is a big plus Bonus Prior work experience in a startup or venture-backed company is a big plus. Benefits Generous compensation packages including equity Medical Insurance Parental Leave Sabbatical leave (After 4 years of service) Investors and Funding Arrcus has raised over $125M in funding from top tier Venture Capital firms(VCs) such as Lightspeed Venture Partners, General Catalyst, and Clear Ventures as well as strategic investors such as Liberty Global, SoftBank Corp, and Samsung Next. For more information, go to www.arrcus.com or follow @arrcusinc . Equal Opportunity At Arrcus, we re proud to be an equal opportunity employer We realize the key to creating a company with a world-class culture and employee experience comes from who we hire and creating a workplace that celebrates everyone. A strong belief of culture addition will propel us forward, together.

. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. . 3-10 years of experience in RTL design and Design Verification implementation for VLSI systems.

This position typically requires at least 2 to 3 years of related IP design or customer experience, but we may also consider candidates with less experience with the right academic background. ASIC design experience with proven design background. Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) and silicon bring-up/characterization in a system environment. Domain knowledge of at least one of the following protocols: PCI Express SERDES Serial ATA Good RTL and Gate Level simulation Debug skills Familiarity with Front end implementation like Synthesis, Static Timing Analysis, Logical Equivalence Check Preferred Experience Technical knowledge with any Interface IP such as PCIe, USB, SATA, MIPI, HBM DDR, LPDDR Protocols, Specification, Design, and Implementation flows with Design Compiler, Fusion Compiler and PrimeTrime. Excellent organization skills, excellent communication skills and ability to interact with customers Proven track record in meeting tight schedules and handling multiple projects concurrently

Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers.

You have a keen eye for detail and can identify design/architecture pitfalls across clock/reset domain crossings . Your ability to synthesize designs and ensure RTL and gate equivalence through formality checks is unmatched. You are a collaborative team player, ready to integrate IPs in SoCs/Subsystems and create RTL designs that meet customer needs. If you are ready to leverage your expertise in a role that shapes the future of semiconductor design, Synopsys is the place for you. What You'll Be Doing: Perform RTL Quality Signoff Checks such as LINT, CDC, and RDC. Understand design/architecture and develop timing constraints for synthesis and timing . Run preliminary synthesis to ensure design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates . Integrate IPs in SoCs/Subsystems and create RTL design as per customer needs. Collaborate with cross-functional teams to deliver high-quality RTL designs. The Impact You Will Have: Ensure high-quality RTL Signoff for semiconductor designs. Contribute to the development of cutting-edge semiconductor technologies. Improve design efficiency and performance through effective timing constraints. Enhance the reliability and functionality of SoCs and subsystems. Support customer success by delivering tailored RTL designs. Drive innovation in RTL Design and Verification methodologies.

You are a seasoned professional in RTL Design and Signoff , bringing a wealth of experience and expertise to the table. You have a keen understanding of the complexities of RTL Quality Signoff and are adept at proposing resource requirements to meet project goals. Your leadership skills are top-notch, allowing you to guide a team of engineers through various pre-silicon static verification activities on IPs/Subsystems . You have a strong grasp of design and architecture , enabling you to develop precise timing constraints for synthesis and timing . Your ability to ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products ensures that you stay ahead of the curve. You collaborate effectively with peers to enhance methodology and execution efficiency. Your excellent communication skills facilitate smooth interactions with Synopsys customers, BU AEs, Sales teams, and other stakeholders. With a minimum of 8+ years of experience , you are well-versed in debugging, diagnosing violations, and setting up flows and methodologies for quick RTL Signoff tool deployment . Your technical expertise in LINT, CDC, RDC, and timing constraints development is unparalleled. You are a strategic thinker with a strong understanding of design concepts, ASIC flows, and stakeholder management . What You'll Be Doing: Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Lead a team of engineers to perform various pre-silicon static verification activities on IPs/Subsystems. Develop timing constraints for synthesis and timing while understanding the design/architecture. Collaborate with peers to improve methodology and enhance execution efficiency. Ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers. Work with other Synopsys teams, including BU AEs and Sales, to develop, broaden, and deploy Tool and IP solutions. Set up flows and methodologies to enable quick setup for RTL Quality checks, Synthesis, and Formality. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Ensure high-quality RTL Signoff and design, contributing to the success of Synopsys projects. Lead the team in delivering precise and efficient pre-silicon static verification activities. Enhance the overall execution efficiency of RTL Design and Signoff processes. Enable customers to achieve their goals through the deployment of Synopsys Products and methodologies. Develop and implement innovative solutions for RTL Quality Signoff in the semiconductor industry. Strengthen Synopsys reputation as a leader in chip design, verification, and IP integration. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 8+ years experience in RTL Design and Verification. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise in setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead a team to perform RTL Signoff on complex SoC/IP/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

You are a highly experienced and motivated professional with a solid background in SoC RTL Design . With over 12 years of experience , you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development . You possess a deep understanding of design concepts, ASIC flows, and stakeholder management . Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints . You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables . Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently. What You'll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities . Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 12+ years of experience in SoC RTL Design . Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces . You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards , and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure , sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You'll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage , and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You'll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities.

An experienced and visionary ASIC Verification Engineer, Architect who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL, UCIe etc. You can define and execute Testbench architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What You ll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You ll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 15+ years in relevant domain.

Key Responsibilities: Translate design specifications into comprehensive power specifications and architect UPF files accordingly. Build and refine power intent using Unified Power Format (UPF) at RTL and gate-level, ensuring consistency across synthesis and physical design flows. Perform power-aware checks using CLP and debug issues arising during MV cell insertion such as isolation, retention, and level shifters. Collaborate with Power Aware DV teams to address feedback and enhance the robustness of power intent. Estimate dynamic and leakage power early in the design cycle and generate power reports using tools like PTPX . Monitor and analyze power trends through implementation milestones; highlight mismatches and coordinate resolution with synthesis/PD teams. Partner with SoC, subsystem, and verification teams for accurate delivery of power intent and power estimates across project phases. Drive automation and improve analysis workflows via scripting using TCL, Perl, or Makefiles . Technical Skills: Expertise in creating and validating UPF-based power intent for SoCs with complex power domains In-depth experience in CLP-based RTL/Gate-level validation Strong command of power estimation using PrimeTime PX (PTPX) Solid knowledge of MV logic components and their insertion behavior during synthesis Clear understanding of power optimization techniques for both dynamic and leakage at various design stages Familiarity with Pre-Si/Post-Si power correlation strategies Strong scripting capabilities in TCL/Perl , with experience in managing flows through Makefiles Interested share resume or references to Shubhanshi@incise.in

Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You'll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively

You are an experienced ASIC Digital Design Engineer with a deep understanding of interface protocols such as USB2/3/3.1, PCIe Gen1/2/3/4/5/6, Ethernet, and JESD204B. With a solid background in SERDES/PHY/Controller IP specification and compliance validation, you thrive in dynamic environments where your expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM) is highly valued. You are passionate about delivering high-quality RTL and simulation models, and you excel in developing and reviewing verification plans and environments. Your proactive approach to problem-solving, coupled with your ability to support customers during silicon bring-up and debug phases, makes you an invaluable asset to any team. Your technical prowess is matched by your excellent communication skills, enabling you to effectively collaborate and influence across departments and with external partners. What You'll Be Doing: Developing and reviewing verification plans for SERDES/PHY/Controller IPs. Creating and maintaining verification environments, with a preference for UVM. Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure. Delivering high-quality RTL and simulation models to customers. Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems. Supporting customers with IP integration, silicon bring-up, and debugging issues. Demonstrating Testchip+FPGA system demos to customers and at conferences. The Impact You Will Have: Ensuring the compliance and functionality of our interface IPs with industry protocols. Enhancing the quality and reliability of our silicon solutions for customers. Facilitating smooth customer adoption and integration of our IPs. Contributing to successful silicon bring-up and debugging efforts. Showcasing our technological advancements at industry events. Driving innovation and excellence in digital design and verification processes. What You'll Need: Expertise in one or more interface protocols (e.g., USB, PCIe, Ethernet, JESD204B). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Experience with SERDES/PHY/Controller IP specification and compliance validation. Strong background in developing and reviewing verification plans and environments. Ability to deliver high-quality RTL and simulation models to customers.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

Experience in working on validation of ASIC/SoC products. Knowledge of post-silicon features & functional validation for BSPs and Linux Device Drivers. Knowledge of Test case development & implementation for IP's features. Expertise in protocols/interfaces such as USB, PCIe, I2C, SPI, UART, and Ethernet. Knowledge of Software Development & Testing Life Cycles. Strong knowledge of C, Python, Shell, and Bash Scripting. Strong knowledge of Linux Kernel, Boot-Up Process, Linux-Internals, and System Calls. Understanding of Schematics and PCB board design. Experience with version control software such as GIT. Excellent Communication and learning skills.

Position - ASIC Engineer (5+ Years Floor planning , Place and route , Formal verification , Timing closure , Perl / Python / Scripting ) Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and best known methods to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experience. We are looking for high achievers who love challenging environment to join our team.

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelors Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Role & responsibilities Job Title: Mix Signal ASIC/IC Functional safety engineer/manager Job location: Bangalore Work mode: Hybrid Mode of employment: Permanent / Direct Company Payroll OVERVIEW: Seeks a dynamic and experienced Mix Signal ASIC/IC Functional Safety Engineer & Manager to join the Sensor Global Quality Engineering Center within its Sensors Quality Organization. This role focuses on ensuring the compliance to Functional Safety requirements of sensor products from project definition to production release for Automotive and Industrial & Transportation (ICT) markets. This role will engage with various Engineering Centers of Expertise and manufacturing plant globally. It is a strategic role to support Sensor Technology roadmap based in our growing Global Design Center Bangalore India. KEY RESPONSIBILITIES: Functional Safety for New Technology Development: Ensure that functional safety requirements are met from project definition to production launch according to company stage gate procedure. Provide guidance to project stakeholders to adhere to ISO26262 standards Negotiate and mutually agree on required safety goals with customers (DAI) Contribute to the development of technical safety Concepts per ISO26262. Deliver Functional safety Work Products as per ISO26262 such as Safety Plan, HARA, FSR/C, TSR/C, FMEDA at hardware level (IP block/Gate). Review gate exits and release Functional Safety documentation (Safety Case) to enable production launch. YOU MUST HAVE Functional Safety Certification Experience: Minimum of 10 Years Experience in functional safety at hardware level SoC, ASIC, IC Successful release in production of project of at least ASIL C level . Proficiency with all Functional Safety tools from safety plan to safety case, including SPFM, LFM metrics Master FDMEA and FIT calculation Knowledge of Quality Standards: Familiarity with ISO 9001, AS 9100, IATF 16949 Strong English communication skills Customer & Leadership Engagement: Ensure efficient communication with customers and leadership team on functional safety related topics Anticipate and manage escalations effectively. Process & Continuous Improvement Management: Inspire a Zero-Defect mindset by ensuring data-driven problem-solving and improvement initiatives. Evaluate project outcomes, identify areas for improvement, and suggest enhancements to processes. WE VALUE Six Sigma Green Belt or Black Belt certification Experience in Cybersecurity ISO 27001 or ISO/SAE 21434 Experience participating to VDA audits, IATF audits EDUCATION Bachelor or Master in Engineering or related discipline Interested candidate please apply here. Also share your profile to chidananda@manpower.co.in; Best Regards, HR Team, Manpower Group Preferred candidate profile

Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

Requisition ID P tracker ID HM Location Skill Level YTR YTR Richard Liu Bangalore Business Analyst Level 2 Required: 3 years of relevant experience Bachelor degree in a related field Experience with logical data modeling for the representation and storage of trades Strong analytical skills Ability to propose creative solutions to complex messaging and modeling problems Basic knowledge of SQL Excellent technical writing and verbal communication skills to document and explain models to multiple stakeholders Influencing and relationship building across global teams Ability to influence external teams to conform to models/standard Project management/coordination skills Ability to multitask and operate in a fast-paced environment Specification/requirements gathering Desired: Experience with FIX messaging protocol Logical data modeling using ER diagramming Experience with the FIX messaging protocol Basic knowledge of either DB2, Greenplum, kdb In depth front to back knowledge of at least one asset class, eg Equity cash or Listed Derivatives Experiences with Asia cash and LD trading regulatory data requirements, e.g. SFC DSOL, ASIC, will be preferred

Job Title: Product Stewardship Specialist I Summary: This position is responsible to ensure continuity and growth of the business through compliance with regulations applicable to the products and business activities through development of technical solutions to a wide range of difficult challenges. This requires ensuring product compliance in meeting the business and growth needs. It also requires driving best practices that are efficient and consistent with Global Product Stewardship goals, objectives, policies, and procedures. Works directly with all levels within Momentive businesses and direct resources with appropriate expertise in supporting product compliance and registrations with significant impact on the product launch success in alignment with other regions, customer interface, new end uses for existing products, new product introduction and development, product portfolio and strategic risk assessments. In addition, this role will be responsible for Momentive product customer communications and supporting the Regulatory Strategy Forum and Application Review processes. Responsibilities Include: Project Management Responsible to coordinate and lead with minimal guidance on defined scope projects within Product Stewardship . Responsible for responding to complex customer inquiries, topics, and questionnaires. Responsible for data management and identification of data inconsistencies and gaps within core function . Responsible to identify and protect confidential product stewardship information. Execution Execute focused projects independently with minimal support . Participate in multiple activities without compromising delivery . Provide accurate , consistent, and on-time responses to internal and external customers. Independently research and collect information in support of compliance related programs . Collaboration & Communication Share information cross-functionally and ensure appropriate SMEs and stakeholders are included. Routinely share information and learnings within PS Team and in meetings. Support multiple cross-functional and PS Team regulatory needs and activities in Sprint model . Regulatory Skills Responsible for providing comprehensive information on regulatory knowledge and industry expertise . Identifies and executes necessary actions related to changing chemical regulations within Product Stewardship . Responsible to identify and protect confidential product stewardship information . Technical Skills Responsible for applying concepts and principles with proactive use of existing technology . Identify opportunities for new templates and process improvements . Responsible for learning and training others on SME topics within the PS organization . Process Skills Proactively compile information to demonstrate and describe the benefit to the organization on defined process improvement projects . Lead small process improvement projects with support . Knowledge Support silicone chemistry training in specialized areas and industry practices, techniques, and standards. Work independently with SAP EHS Module and relevant business tools to provide basic training to others. Qualifications: The following are required for the role Technical degree in Engineering, Pharmacy, Chemistry, Biology, Life Science, Environmental Science, Industrial Hygiene, Safety Engineering, Public Health or equivalent Minimum 6 to 8 years, relevant experience in the chemical or related industry in the area of Product Stewardship and Regulatory Compliance/ Environmental Health and Safety/Occupational Safety and Industrial Hygiene or other applicable experience Business Acumen, ability to inform business and influence decision making. B asic chemistry skills related to product chemistry . Ability to work cross-functionally and proactively establish connections. Excellent interpersonal skills . Ab le to work, lead, and manage across functions in a global organization with matrix reporting structure. Strong working knowledge of product regulatory legislation and regulation in the regions/countries within job scope . Flexibility to focus on chemistry-related topics, customer support and fulfilling legal requirements. Proven organizational and project management skills . Able to manage multiple priorities simultaneously. Excellent English verbal and written communication and presentation skills. Computer literate in standard office systems . A vailab le fo r early morning or late evening global calls as needed. Able to travel , including internationally, as needed and work in a chemical plant environment. Customer service experience Preferred Qualifications: Experience in Silicones industry and/or with highly regulated end use markets in which Momentive operates (personal care, agriculture, healthcare, food contact, etc.) / Product Line Knowledge. Experience working directly with internal and external customers, understanding, and showing a high level of commitment and response to their needs. Six Sigma Blackbelt or Greenbelt SAP EHS experience. Project Management skills . What We Offer: At Momentive, we value your well-being and offer competitive total rewards and development programs. Our inclusive culture fosters a strong sense of belonging and provides diverse career opportunities to help you unleash your full potential. Together, through innovative problem-solving and collaboration, we strive to create sustainable solutions that make a meaningful impact. Join our Momentive team to open a bright future. #BePartoftheSolution About Us: Momentive is a premier global advanced materials company with a cutting-edge focus on silicones and specialty products. We deliver solutions designed to help propel our customer s products forward products that have a profound impact on all aspects of life, around the clock and from living rooms to outer space. With every innovation, Momentive creates a more sustainable future. Our vast product portfolio is made up of advanced silicones and specialty solutions that play an essential role in driving performance across a multitude of industries, including agriculture, automotive, aerospace, electronics, energy, healthcare, personal care, consumer products, building and construction, and more. Momentive believes a diverse workforce empowers our people, strengthens our business, and contributes to a sustainable world. We are proud to be an equal opportunity employer . Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any characteristic protected by law. To be considered for this position candidates are required to submit an application for employment and be of legal working age as defined by local law . An offer may be conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations . Note to third parties: Momentive is not seeking or accepting any unsolicited assistance from search and selection firms or employment agencies at this time.

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary powercontrol signals integration. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Your Profile You are best equipped for this task if you have: Must have worked in ASIC Design flow, with ASIC experience of upto 5years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for ASIC development using Verilog. Must be familiar with LINT (LEDA / Spyglass) , Clock-Domain-Crossing analysis, UPF, MVRC, Synthesis , Timing constraints and debugging STAreports. Strong mindset towards automation of repetitive work. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Moderate Individual Contributor with Freedom to Act, Team work and Learn Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone.