776 Asic Jobs - Page 2

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /masters degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements2+ years of experience with a Bachelors/ Masters degree in Electrical engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Highly skilled SystemC Modeling Engineer is required to join dynamic and innovative NoC Systems team in Qualcomm Bangalore Design Center. The ideal candidate will have a strong background in digital design and a deep understanding of SystemC for hardware modeling and simulation. This role involves developing and maintaining high-quality SystemC models for complex digital systems, collaborating with cross-functional teams, and ensuring that Qualcomm products meet the highest standards of performance and reliability. Key Responsibilities: Model Development: Design and implementation of SystemC models for digital systems, including processors, memory controllers, and peripheral interfaces. Methodology Awareness of Virtual prototypes and Performance modeling using C++/SystemC/TLM 2.0. Approximately timed and Loosely Timed(LT) style of coding for software development when using Virtual Prototype Verification: Development and executution of testbenches to verify the correctness and performance of SystemC models. Optimization: Optimization of models for simulation speed and resource efficiency. Documentation: Creation and maintenance of detailed documentation for models, testbenches, and verification plans. Collaboration: Work closely with hardware and software engineers to ensure seamless integration of SystemC models into the overall system design. Troubleshooting: Identify and resolve issues in the modeling and simulation process. Research: Stay updated with the latest advancements in SystemC and digital design techniques. Technical Skills Proficient in SystemC and C++. Strong understanding of digital design principles and techniques. Experience with hardware description languages (HDLs) such as Verilog is a plus. Familiarity with simulation tools and environments is a plus. Soft Skills Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Ability to work independently and in a team environment. Attention to detail and a commitment to quality. Preferred Skills Experience with Network-on-chip, high-performance computing and parallel processing. Knowledge of ASIC design. Familiarity with scripting languages (e.g., Python, Perl). Experience with version control systems (e.g., Git). Qualifications: Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5 to 10 years of experience in digital design and SystemC modeling. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Where Technical / Product Publications, Staff Engineer Bengaluru, Karnataka, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 12356 Date posted 07/24/2025 Share this job Email LinkedIn X Facebook Who we are: Synopsys (NASDAQ: SNPS) is the biggest ASIC EDA software company and the 2nd largest semiconductor IP provider in the world. Founded in 1986, $5B+ Synopsys employs 20,000+ headquartered in Mountain View, California, located globally in over 25 countries with 113+ offices throughout North America, Europe, Japan, Asia, and India. We enable companies to create the leading-edge micro-chips found in the latest smartphones, data center servers; and automobile smart systems. Synopsys is committed to fostering an environment that treats people with respect, honesty, and professionalism. We only want the best of the best to join our team. Be ready to produce results; bring innovation, creativity, and passion to work every day. What you will do: As a tech savvy and passionate Technical Writer in the Solutions Group at Synopsys, you will be part of a group responsible for developing and writing user documentation for various Digital and Mixed Signal IPs. You will have an opportunity to work across the various IP product lines of USB, PCIe, Ethernet, DDR, HDMI, MIPI etc., You will be responsible for planning, organizing, writing, and editing the technical specifications, engineering schematics, application notes, and user guides. You will be interfacing with our Design Engineering team to collect the raw content of technical specification and to effectively transform this into user consumable collateral by following the doc-processes. You will work independently, interacting, and collaborating with multi-site teams and you will deliver high quality documentation by demonstrating strict adherence to the style guide and other doc-processes followed by the group. As a writer, you will collaborate with other teams and have a significant and immediate impact on all customer documentation produced and the documentation roadmap. Hard skills we are looking for: Degree or masters in any electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. Other technical disciplines also considered. 3-7 years technical writing experience in software or hardware industry Excellent problem-solving skills; strong logical reasoning and solution-oriented Experience with authoring tools such as FrameMaker Excellent English writing and speaking skills Soft skills we are looking for: Has excellent communication and interpersonal skills Energetic and capable of learning new technologies as necessary Team player and able to work independently with minimal supervision You care (about others, about doing a good job, about details) You take ownership of projects and tasks assigned to you with little to no supervision and have pride in quality work done correctly the first time Advantageous skill areas that will give you the edge: Familiarity with Verilog and ASIC digital design flows TCL Structured FrameMaker. XSLT and XPATH Structured FrameMaker EDD and DTD DITA, DocBook, or IP-XACT XML schemas FrameScript, ExtendScript, or FDK DITA Open Toolkit At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Analog Design, Sr Engineer Bengaluru, India Engineering Analog Design, Sr Engineer Bengaluru, India Engineering R&D Engineering, Sr Engineer Bengaluru, India Engineering

Where ASIC Physical Design, Manager Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12252 Remote Eligible No Date Posted 24/07/2025 Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the semiconductor industry, you thrive in dynamic, fast-paced environments and have successfully led teams through multiple tapeouts at least two of which you have completed independently. Your hands-on knowledge of physical design implementation, timing closure, power optimization, and physical verification using industry-standard tools sets you apart as a technical authority in your field. You bring a holistic understanding of the chip design flow, and your familiarity with both front-end and back-end design methodologies allows you to bridge gaps across the development cycle. Your leadership style is inclusive and motivating, fostering a culture of innovation, collaboration, and continuous learning within your team. You are adept at project and technical management, ensuring milestones are met while maintaining the highest standards of quality and efficiency. Your communication skills are exceptional, enabling you to interact effectively with cross-functional teams, foundry partners, and customers alike. You are driven by the excitement of building next-generation embedded memory products and thrive on solving complex engineering challenges. You value diversity, are committed to mentoring others, and believe in empowering your team to achieve their best. If you are ready to make a tangible impact on cutting-edge silicon validation and design, Synopsys offers the perfect environment for your ambitions. What You ll Be Doing: Leading and mentoring a high-performing team responsible for physical design implementation and tape out of advanced ASICs and test chips. Driving end-to-end chip design flow, from RTL to GDSII, ensuring successful execution of multiple projects. Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools. Collaborating closely with front-end design, silicon validation, and software teams to deliver robust and efficient solutions. Managing project schedules, resource allocation, and risk mitigation to ensure timely and successful tape outs. Acting as the technical point of contact for foundry interactions and customer communications throughout the design and post-silicon support phases. Championing best practices in design methodology, quality assurance, and continuous process improvement. The Impact You Will Have: Delivering high-quality, high-performance test chips that enable next-generation embedded memory products. Accelerating time-to-market for Synopsys customers by ensuring robust and timely tape outs. Enhancing the company s technical reputation through successful project delivery and customer satisfaction. Driving innovation in physical design methodologies and tool flows to optimize efficiency and reliability. Mentoring and developing the next generation of engineering talent within the organization. Strengthening key partnerships with foundries and customers through proactive engagement and technical leadership. Contributing to the strategic direction of the Silicon Validation Design Team and influencing future product development. What You ll Need: 10-15 years of hands-on experience in ASIC physical design, with at least 5 years in a leadership role. Proven track record of multiple successful tape outs (minimum two completed independently). Expertise in physical design implementation, timing closure, power and physical verification using industry-standard EDA tools. Strong understanding of the complete chip design flow, from RTL to GDSII. Experience in project technical management, people management, and cross-functional collaboration. Knowledge of front-end design and RTL methodologies is a significant plus. Who You Are: Inspirational leader with a collaborative and inclusive approach to team management. Excellent communicator, able to articulate complex technical concepts to diverse audiences. Analytical thinker with strong problem-solving skills and a detail-oriented mindset. Adaptable, proactive, and comfortable making decisions in fast-paced, evolving environments. Committed to continuous learning, mentoring, and fostering a culture of growth and innovation. The Team You ll Be A Part Of: You will join the Silicon Validation Design Team, a passionate group dedicated to designing and developing test chips for embedded memory products. Our unique strength lies in owning the process end-to-end from RTL to GDSII tape out and post-silicon support while engaging directly with foundry partners and customers. We pride ourselves on innovation, technical excellence, and a collaborative spirit that drives continuous improvement and customer success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people It requires a consistent and committed practice, something we call the Juniper Way ASIC Engineer Design Silicon Systems Technology Group (SST) seeks ASIC Design Engineers to develop next generation of ASICs for new core routers, switches, and firewalls Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems You will have a significant opportunity to interact with system design teams across geographies Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture Thus, you set your own limits for learning, achievements and rewards Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 5+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required

Job description To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Responsibilities You will be part of the platform team, responsible for developing platform software in the areas of: Board-bring up related experience. 10G, 40G, 100G and 400G interface related platform software like interface drivers etc. Platform infrastructure related software like Chassis/line card, fabric, Optics, HA, etc. Device Drivers & SOC SDK Integrations You will be responsible for these product developments in the platform area in either JunOS or Junos Evolved based software architecture. In addition to the design & development activity, you are required to work closely with system and solution test teams to ensure products/solutions delivered are of the highest quality. You will be required to work closely with Juniper Technical Assistance Team to provide engineering assistance in supporting critical customer escalations for customer deployments. Requirements BTech / MTech in CS/CE or related field with 14+ years of proven experience. In-depth knowledge of data networking, e.g., TCP/IP, Ethernet, Switching, Routing etc. In-depth knowledge of kernel device drivers, system bring-up, FreeBSD/Linux internals. Understanding of Ethernet, OTN, SONET etc. technologies. Strong technical, analytical, and problem-solving skills. Strong in C, C++ programming, OO analysis & design, data structures and system debugging skills. Good understanding of firmware, hardware level details for Optics, PCIe, SPI, I2C, FPGA, CPLD, MDIO, Flash Driver. Prior software development experience on networking products or board bring-up experience is MUST.

Job description You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites. Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%) Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity. (25%) Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%) Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%) Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%) Required Skills: ASIC Verification using System Verilog Experience in constrained-random verification is a strong plus Experience with verification methodology like OVM/VMM/UVM Perl/Tcl scripting is strongly preferred Experience verifying networking protocols such as Ethernet is desirable Strong problem solving and ASIC debugging skills MSEE or BSEE is required with at least 12 years of ASIC Verification Experience.

Job description Preparation of test plan and test execution of the feature.. Automation of test framework and test cases using python and REST APIs, and Robo Framework. Work with different software releases to verify the bugs and provide support to the development team to reproduce the problems.. Attend any critical customer/partner escalation issues.. Relevant Technolgy understanding and Testing experience in L2 Protocols xSTP, LACP, LLDP, IGMP Snooping, MacSEC, VPLS, EVPN-VXLAN, COS/QOS, RED/WRED, GLB, DLB, PFC, ECN. Experience using Traffic Generator for manual as well automation using Spirent/IXIA Traffic Generator. Automation Skillset with Python and Robo Framework / or any scripting language Perl/TCL/Python. Advanced level of expertise in handling Customer escalations, and Trouble shooting the reported issues, and effectively collaborate with larger team accounts, sales and engineering and ensuring the customer issues are resolved. Min 6 to 8 Yrs Experience in the Networking Technology domain.

Job description To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Key Responsibilities: Testing & Automation : Design, develop, and implement end-to-end testing based on best practices. Deliver automated test scripts using agile methodologies and advanced techniques. Validate functional, scale, and performance tests across technologies on networking products. Customer Solution Alignment : Understand and develop test strategies based on software functional specifications and customer certification processes. Collaborate with product development and architecture teams to align testing with customer network priorities. Cross-Functional Collaboration : Work with geographically distributed teams and diverse cross-functional groups to execute test scenarios. Foster relationships with senior leadership to align business objectives with project outcomes. Problem-Solving & Issue Replication : Analyze and troubleshoot software issues identified during test executions. Replicate and resolve customer-found issues, providing root-cause analysis and corrective actions. Innovation & POC : Provide proof of concepts (POCs) for customer use-case scenarios to demonstrate feasibility. Highlight emerging technologies and brainstorm enhancements for product deliverables. Tools & Technologies: Networking Expertise : Strong understanding of protocols like OSPF, BGP, MPLS, EVPN-VXLAN, L2VPN, etc Automation Proficiency : Advanced skills in Python, Linux, and automated test execution tools. Test Equipment : Hands-on expertise with Spirent, Ixia, and their automation tools. Domain Knowledge : Datacenter, Service Provider, and Enterprise environments. Networking Concepts : CLOS Architecture, High Availability, Multicast, Layer 2/3 Technologies, TCP/IP . Preferred Qualifications: For non-Juniper candidates : JNCIP or equivalent certifications from Cisco/Arista in Datacenter/Service Provider domains. For Juniper-experienced candidates (4+ years) : JNCIS or higher certifications. This role requires a self-starter with excellent problem-solving, communication, and multitasking skills, making it a critical contributor to customer-centric, technology-driven outcomes. Minimum Qualifications: 4-7+ years of relevant experience

Job description Design and develop forwarding software for high-performance networking products, with an emphasis on quality, efficiency, and robustness. Focus on key areas of packet forwarding engines (PFE), including L2/L3, MPLS, EVPN, CoS, and ACLs, to drive advanced functionality. Work closely with cross-functional teams to enhance and support the architecture of router and switch products, contributing to our innovative technology. Troubleshoot complex issues within customer deployments and lab environments, leveraging strong debugging and core file analysis skills to deliver optimal solutions. Ensure process and quality focus to meet the high standards of our networking products. Qualifications Experience : 3+ years in the networking industry, with experience in router or switch companies preferred. Technical Expertise : Proficiency in one or more of the following areas: Packet Forwarding Engine (PFE) : Expertise in L3, MPLS, EVPN, CoS, ACL, and more. Router/Switch Architecture : Strong understanding of network processor-based product architecture. Broadcom ASICs : Experience with Broadcom Qumran or Jericho is a significant advantage. Coding & Debugging : Proficiency in coding, particularly in C/C++, with strong debugging and core file analysis skills. Networking Knowledge : Familiarity with IP, MPLS, Bridging, OAM, L2/L3 forwarding, VPLS, Multicast, QoS, L2VPN, L3VPN, Filters, etc. Computer Science Fundamentals : Deep understanding of computer architecture, data structures, and programming best practices.

Job description Responsibilities In this role, you will: Design and develop forwarding software for high-performance networking products, with an emphasis on quality, efficiency, and robustness. Focus on key areas of packet forwarding engines (PFE), including L2/L3, MPLS, EVPN, CoS, and ACLs, to drive advanced functionality. Work closely with cross-functional teams to enhance and support the architecture of router and switch products, contributing to our innovative technology. Troubleshoot complex issues within customer deployments and lab environments, leveraging strong debugging and core file analysis skills to deliver optimal solutions. Ensure process and quality focus to meet the high standards of our networking products. Qualifications Experience : 3+ years in the networking industry, with experience in router or switch companies preferred. Technical Expertise : Proficiency in one or more of the following areas: Packet Forwarding Engine (PFE) : Expertise in L3, MPLS, EVPN, CoS, ACL, and more. Router/Switch Architecture : Strong understanding of network processor-based product architecture. Broadcom ASICs : Experience with Broadcom Qumran or Jericho is a significant advantage. Coding & Debugging : Proficiency in coding, particularly in C/C++, with strong debugging and core file analysis skills. Networking Knowledge : Familiarity with IP, MPLS, Bridging, OAM, L2/L3 forwarding, VPLS, Multicast, QoS, L2VPN, L3VPN, Filters, etc. Computer Science Fundamentals : Deep understanding of computer architecture, data structures, and programming best practices.

Job description Must have Skills BS/MS in CS/CE or similar field, with a minimum of 2-8 years of software development experience Proficient in C, C++ programming and debugging Experienced in Unix/Linux systems with proficiency in user-space processes, kernel, socket programming, inter-process communication Analytical Skills: Excellent analytical and problem-solving abilities Teamwork: Ability to work effectively in teams Interpersonal Skills: Strong interpersonal skills Good to have skills Internet Protocols: TCP/UDP/IPv4/IPv6 Domain Knowledge: Service Provider Technologies, Access and Aggregation Deployments, Metro, Mobile Backhaul. Networking Protocols: Hands on knowledge on L2/L3 Protocols, CoS/QoS, ACL/Firewalls. Experience with application development on XGS or DNX family like Jericho, Jericho2 will be a plus. Outline primary role responsibilities You will be responsible for product development of cutting edge platforms for next gen Access and Aggregation Deployments, Metro, Mobile Backhaul with JunOS or Junos EVO software architecture. In addition to the development activity, you are required to work closely with product management, system and solution test teams to ensure products/solutions delivered are of the highest quality. You will be required to work closely with Juniper Technical Assistance Team for providing engineering assistance in supporting critical customer escalations for customer deployments.

Job description Work with internal Design teams and Methodology teams to successfully Lead/implement Physical Designs of multiple blocks of Complex ASICs . The position requires good understanding of the physical design flow from RTL to GDS several chips tapeout experience. The successful candidate should possess in-depth knowledge experience in physical synthesis, design planning, floor planning, place route, static timing analysis and design closure physical verification Responsibilities Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis fixes, Low Power solution development implementation. Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools flow, etc Work closely with the methodology team to solve the implementation challenges provide inputs to improve the Physical design flow. Experienced in design automation. Understanding of Timing constraints, SI prevention, Power reduction. Must have prior experience with Synopsys/Cadence/Mentor place and route tools. Must have completed design in 16nm and or 7nm.. Proficient in Unix/TCL/Perl. Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability. Minimum Qualifications 4+ years experience in ASIC physical design Experience with block implementation, extraction, timing and or full-chip designs Strong communication skills Strong hands-on TCL/Perl development skills Preferred Qualifications Experience as a full-chip floor planning, routing, or timing lead for a large silicon project Track record of taping out complex chips on advanced process nodes

As a Functional Verification Engineer at AMD in Hyderabad, you will be responsible for verifying the functionality of complex System on Chip (SOC) designs using industry-standard verification methodologies. With 4-10 years of experience, you will play a key role in ensuring the quality and reliability of ASIC designs. You should be proficient in UVM (Universal Verification Methodology) and have a strong command of Verilog or SystemVerilog. Additionally, knowledge of AMBA Bus Protocols is essential for this role. Your expertise in functional verification, design verification (DV), and ASIC verification will be crucial in meeting the verification goals of the projects. Working closely with cross-functional teams, you will have the opportunity to contribute to cutting-edge technologies and innovative solutions. This position requires immediate to 45 days notice period availability. If you are passionate about verification engineering and have a solid foundation in AMBA, SystemVerilog, SOC, Verilog, and other relevant skills, we invite you to join our team at AMD and be part of our dynamic work environment. Join us in shaping the future of technology with your verification expertise.,

RTL/Integration- Design Engineer Work Location : Bengaluru, Whitefield Qualification : 5-10 years full-time experience in IP hardware design Mode of interview : Virtual Availability to join: candidates who can join in 30-45 Days are preferred. Normal Working Hours, 5 days a week Work Mode : Work from Office The Project and role : As a member of the Computing and Graphics group , you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. The Person: The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Preferred Experience: Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Functional Skills Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Were hiring a talented RTL Design Engineer to join our team in Hyderabad and contribute to advanced ASIC/SoC projects. Key Responsibilities: Perform RTL integration for ASIC/SoC designs Debug CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) violations Analyze and resolve timing and CLP (Clock Level Planning) issues Apply strong digital design fundamentals in RTL development Tackle complex design problems with excellent debugging skills Requirements: 3+ years of experience in RTL design and integration Solid foundation in digital logic design Strong problem-solving and debugging abilities

Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies. Qualifications Must have Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Working experience (20+ years) in IO including 5+ years as a project leader S

Dear Applicant, Greetings of the day!!! ACL Digital is actively hiring for experienced Senior Software Developer -SONiC/SAI with strong networking operating system development background to join our dynamic team. Job Requirement - Senior Software Developer -SONiC/SAI Preferred Qualification: 5+ Years Experience (Flexible work mode - Remote/Onsite/Hybrid) Hands-on experience with Dockers Knowledge of SONiC SAI for development of new features and integration Hands-on experience with Redis-DB Strong knowledge and hands-on experience network ASIC architecture and SDK development/integration Hands-on experience with open source Layer 2 protocols (teamd, STP) and L3 (FRR - BGP, OSPF) networking protocols Architectural knowledge of data center design (Leaf/Spine, CLOS) and distributed systems Ability to take a project from scoping to actual delivery meeting customer requirements Excellent written and communication skills with an ability to influence peers and customers Basic Qualification: 5+ Years of Software development including Programming experience with C/C++/Python/go Experience in Design, development and testing of Data Center Networking infrastructure and protocols Good understanding of data structures, algorithms and computer science fundamentals Hands on experience with linux TCP/IP networking, Netlink Immediate joiners are preferred, apply here or connect me zahid.h@acldigital.com

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Ciscos core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Ciscos ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Work with the team on Verilog RTL and scripted flow implementation of the specified Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design. Work with the team on Verilog testbench implementation of the specified verification tests for DFT features and use case. Work with the team on automation scripts intended for robustness of implementation quality and improvement of efficiency. Minimum Qualifications: Bachelors or a Master s Degree in Electrical or Computer Engineering required with at least 2+ years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Preferred Qualifications: VLSI circuit physical behaviors in silicon (electrical migration, temperature/voltage variation effects). Basic timing concepts, including setup and hold, metastability. Some EDA tools usage experience Strong verbal communication skills and ability to thrive in a dynamic environment Scripting/coding language: Tcl, Python, Perl, or c/c++. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we re "old" (36 years strong) and only about hardware, but we re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hairDon t care. TattoosShow off your ink. Like polka dotsThat s cool. Pop culture geekMany of us are. Passion for technology and world changingBe you, with us! Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidates hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

Amazon Lab126 is an inventive research and development company that designs and engineers high-profile devices like the Kindle family of products. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc. Since then, we have worked to produce best-selling e-readers and tablets, as well as new inventions like Echo line of products, Fire TV and Fire phone. What will you help us create As a Signal Integrity Engineer, you will be part of Validation team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for Signal Integrity aspects, compliance, and interoperability of package substrate, PCB, Cable solutions and system-level SI for interfaces like PCIe, DDR, Clocks etc. You will also be responsible for contributing to package and platform design guideline development. You will work closely with multi-disciplinary groups including Board Design, System Architects, IP developers, and Design Engineering, to verify and deliver complex, high volume SoCs that enable development of world-class hardware devices. In this role, you will be: Responsible for defining the design guidelines for internal and external design teams and delivering reference simulation docs for customers Performing modeling of package substrate/PCB channels elements in 3D/2D EM simulation tools. Working with silicon designers, platform designers, package designers, electrical validation teams, etc. to support interconnect and interface performance requirements. Reviewing and evaluating package and board design and providing review feedback. Responsible for providing power delivery solutions across platform, package and SOC level Definition of worst-case currents and voltage drop scenarios, MIM/decoupling allocation, grid choices and analysis, droop control, SOC ESD compliance, On-die droop detectors, usage of on-die delivery solutions like VR, LDO, and Power gates. Bachelors in Electrical or Computer Engineering/Computer Science 6+ years in working on validation of ASIC/SoC products High speed serial interface analog building blocks, protocol, specifications and test methods Familiarity with Simulation tools (ADS, HFSS, PowerSI, PowerDC, Hyperlynx) to execute SI-PI simulations is required. Experience with performing measurement, and correlating measurements to simulations. Experience with modeling and simulation of high-speed interface interconnects/channel. Excellent analytical and problem solving skills Masters in Electrical or Computer Engineering/Computer Science Understanding of Power & signal integrity concepts such as differential impedance, jitter, insertion loss, return loss, termination, etc. Scripting experience in any programming language (C++, Python, PERL, MATLAB) to develop automation scripts is a plus. Experience in Analog IP Characterization (SerDes, PLL, DDR) is desirable. Good understanding of High-Speed Analog/Digital Circuits, VLSI, semiconductor physics

Where Technical / Product Publications, Staff Engineer Hyderabad, Telangana, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 7482 Date posted 07/23/2025 Share this job Email LinkedIn X Facebook Alternate Job Titles: Senior Technical Writer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an energetic, experienced, and organized writer passionate about cutting-edge technology. With a keen eye for detail and a knack for making complex topics accessible, you have honed your skills over 3-5 years in the software or hardware industry. Your proficiency with authoring tools like FrameMaker and Oxygen, combined with excellent problem-solving abilities, makes you a standout in your field. You excel in communication, both written and verbal, and thrive in a collaborative environment where you can work independently with minimal supervision. Your dedication to quality and your ability to learn new technologies quickly set you apart. You take pride in your work, care about others, and are committed to doing a good job. Familiarity with semiconductor design flows and tools such as Structured FrameMaker, Oxygen editor, and XML flows is a plus. What You ll Be Doing: Plan, organize, write, and edit various types of customer documentation. Collaborate with world-class engineers to create essential customer documentation in dynamic formats. Empower customers to design-in and optimize Synopsys products through clear, concise documentation. Translate complex technical information into user-friendly content. Ensure documentation meets industry standards and is easily accessible to global customers. Continuously update and maintain documentation to reflect product updates and new features. The Impact You Will Have: Enhance customer satisfaction by providing clear and comprehensive documentation. Facilitate the adoption and optimization of Synopsys products by global customers. Contribute to the overall success of Synopsys by ensuring high-quality documentation. Support the development of innovative solutions through effective communication. Help maintain Synopsys reputation as a leader in semiconductor IP and EDA software. Drive continuous improvement in documentation processes and standards. What You ll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. Other technical disciplines also considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solving skills and strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Exceptional English writing and speaking skills. Who You Are: Excellent communication and interpersonal skills. Energetic and capable of learning new technologies as necessary. Team player who can work independently with minimal supervision. Detail-oriented and committed to producing high-quality work. Proactive and takes ownership of projects and tasks. The Team You ll Be A Part Of: You will join a dynamic, inclusive, and diverse team of talented professionals committed to innovation and excellence. Our Technical Publications team works closely with engineers to create documentation that empowers our customers and drives the success of Synopsys products. We value collaboration, creativity, and continuous improvement, and we are dedicated to fostering a supportive and engaging work environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Analog Mixed-Signal Design Engineer Noida, India Engineering ASIC Digital Verification Engineer, Staff Engineer Moreira, Portugal Engineering EMEA HR Operations Specialist Porto Salvo, Portugal People

Where ASIC Physical Design, Sr Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12343 Remote Eligible No Date Posted 23/07/2025 Alternate Job Titles: ASIC Physical Design Engineer Place & Route Engineer Sr. Physical Design Specialist We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a strong background in ASIC physical design and a keen interest in advancing semiconductor technology. You thrive in collaborative, fast-paced environments and are motivated by technical challenges that push the boundaries of what s possible in chip design. With your foundational education in electronics or electrical engineering, you have honed a solid understanding of CMOS and submicron ASIC flows, working on advanced technology nodes such as 28nm, 16nm, 14nm, 10nm, and 7nm. You possess hands-on experience with industry-leading EDA tools, including Synopsys ICC-II/FC, Design Compiler, PrimeTime, and Cadence Innovus, and are adept at developing, optimizing, and verifying robust ASIC design flows. Your curiosity drives you to stay on top of the latest methodologies, and your analytical mindset ensures you can solve complex problems with innovative solutions. You are comfortable taking ownership of tasks, whether it s developing flows, performing timing analysis, or releasing production views for IP. You communicate clearly, collaborate effectively, and are committed to delivering high-quality results with attention to every detail. You believe in continuous improvement, proactively seeking ways to optimize power, performance, and area (PPA) while maintaining the highest standards of quality. Most importantly, you are excited about making an impact in a global team that values diversity, learning, and technological excellence. What You ll Be Doing: Developing and optimizing ASIC design flows to build and verify standard cell libraries, ensuring the best possible Power, Performance, and Area (PPA) with uncompromised quality. Creating and maintaining Place & Route (P&R) methodologies using industry-standard tools such as Synopsys ICC-II/FC and Cadence Innovus. Releasing P&R production views for IP, ensuring readiness for downstream design and integration teams Conducting thorough physical verification (DRC/LVS), timing analysis (STA), and addressing design closure challenges across advanced technology nodes. Collaborating with cross-functional teams to integrate design flows, improve automation, and resolve technical issues throughout the ASIC lifecycle. Implementing and validating low-power design concepts using UPF/CPF formats, and ensuring robust power analysis and planning. Generating and managing technology files, library views (Milkyway, NDM), and deliverables such as LEF, DEF, GDS for standard cell libraries. The Impact You Will Have: Enable the creation of high-performance, energy-efficient silicon chips that power next-generation applications and devices. Drive improvements in PPA and overall design quality, directly influencing customer satisfaction and product competitiveness. Ensure timely and robust release of IP production views, accelerating time-to-market for Synopsys customers. Advance the state-of-the-art in physical design methodologies, contributing to Synopsys leadership in the semiconductor industry. Collaborate cross-functionally to share best practices and foster a culture of continuous improvement and innovation. Support the successful deployment of Synopsys tools and flows in real-world customer projects, reinforcing our reputation for technical excellence. What You ll Need: Bachelor s or Master s degree in Electronics or Electrical Engineering (or equivalent) from a reputed university. 1-2 years experience in ASIC design, with hands-on exposure to advanced process nodes (28nm, 16nm, 14nm, 10nm, 7nm) and multiple foundries. Strong understanding of CMOS, ASIC flow in submicron nodes, and expertise in Place & Route, physical verification (DRC/LVS), and timing analysis (STA). Proficiency with Synopsys (ICC-II/FC, Design Compiler, PrimeTime) and Cadence (Innovus, RC/Genus) EDA tools. Experience with all stages of the ASIC design flow, including Synthesis, DFT, timing analysis, floor planning, power planning, CTS, ECO flow, STA, and power analysis. Good grasp of low power design concepts, UPF/CPF formats, and standard cell library view generation processes (Milkyway, NDM). Who You Are: Analytical thinker with strong problem-solving skills and meticulous attention to detail. Effective communicator, able to articulate complex technical concepts to diverse audiences. Collaborative team player who thrives in a multicultural and multidisciplinary environment. Self-motivated, adaptable, and eager to learn new technologies and methodologies. Proactive in identifying areas for improvement and driving innovative solutions. The Team You ll Be A Part Of: You ll join a dynamic, inclusive team of physical design and ASIC implementation experts dedicated to developing world-class design flows and methodologies. Our team collaborates closely with IP development, CAD, and validation groups, sharing knowledge and driving best practices across the organization. We value open communication, continuous learning, and a passion for technical excellence, and we are committed to supporting each other s growth and success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

About Us: Tessolveoffers a unique combination of pre-silicon and post-silicon expertise toprovide an efficient turnkey solution for silicon bring-up, and spec to theproduct. With 3200+ employees worldwide, Tessolve provides a one-stop-shopsolution with full-fledged hardware and software capabilities, including itsadvanced silicon and system testing labs. Tessolveoffers a Turnkey ASIC Solution, from design to packaged parts. Tessolve sdesign services include solutions on advanced process nodes with a healthy eco-systemrelationship with EDA, IP, and foundries. Our front-end design strengthsintegrated with the knowledge from the backend flow, allows Tessolve to catchdesign flaws ahead in the cycle, thus reducing expensive re-design costs, andrisks. We actively invest in the R&D center of excellence initiatives suchas 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others.Tessolve also offers end-to-end product design services in the embedded domainfrom concept to manufacturing under an ODM model with application expertise inAvionics, Automotive, Industrial and Medical segments. Tessolve s EmbeddedEngineering services enable customers a faster time-to-market through deepdomain expertise, innovative ideas, diverse embedded hardware & softwareservices, and built-in infrastructure with world-class lab facilities. Tessolve sclientele includes Tier 1 clients across multiple market segments, 9 of the top10 semiconductor companies, start-ups, and government entities. We have aglobal presence over 12 countries with office locations in the United States,India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan,Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. For moredetails, visit www.tessolve.com . Job Overview Briefdescription about the Job. Job Location : Electronic-City, Phase II, Bangalore. What you ll do Design,develop, and maintain high-performance backend services using Java (SpringBoot). Buildand maintain gRPC-based APIs and services for real-time communication betweenmicroservices. Design REST API and rRPC services Manage and optimize Gradle build configurations. Containerize applications using Docker and deploy them on GKE (GoogleKubernetes Engine). Writeand maintain efficient, reusable, and reliable code with unit/integrationtests. UsePostgreSQL for data storage, design schemas, and optimize queries. Setup and manage CI/CD pipelines using Jenkins. Monitor services and troubleshoot production issues using logs and metrics. Collaboratewith frontend, QA, DevOps, and product teams to deliver high-quality features. Who you are Over 8years of hands-on experience in backend software development using Java 11+ andSpring Boot. Proficient in Functional and Reactive Programming paradigms in Java. Solidunderstanding of Java multithreading and concurrent programming principles. Deepexpertise in Spring Security, including implementation of custom securityfilter chains, authentication providers, and role-based access control. Strong background in designing extensible and maintainable codebases usingdesign patterns such as Builder, Factory, and Strategy. Skilled in building and consuming gRPC services for efficientservice-to-service communication. Extensive experience in containerizing applications with Docker and deployingthem on Google Kubernetes Engine (GKE). Proficient in debugging and monitoring applications using Google Cloud Loggingand Monitoring tools. In-depth knowledge of Gradle, including multi-module project setup, taskcustomization, and dependency management. Strong command of PostgreSQL, with expertise in indexing, partitioning, andperformance tuning. Well-versed in configuring and maintaining CI/CD pipelines using Jenkins, witha focus on automation and reliability. Solidgrasp of distributed system architecture, RESTful API design, networkingfundamentals, and application security. Experienced in using observability tools and logs for troubleshootingproduction issues. Committed to writing efficient, reusable, and well-tested code, supported bythorough unit and integration testing. TessolveSemiconductor Private Limited, as well as its affiliates and subsidiaries ( Tessolve ) does notrequire job applicants to make any payments at any stage of the hiring process.Any request for payment in exchange for a job opportunity at Tessolve isfraudulent and should be ignored. If you receive any such communication, westrongly advise you to refrain from making any payments and to promptly reportthe incident to us at hr@tessolve.com. Tessolve is not responsible for anylosses incurred due to such fraudulent activities Home Tessolve is one of the top semiconductorsolutions companies globally. We are end-to-end solution provider, from chipdesign, test, & PCB engineering. Call now!

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Brief description about the Job. Job Location : Electronic -City, Phase II,Bangalore. What you ll do Develop and maintain modern webapplications using React and TypeScript Buildresponsive, accessible, and performant user interfaces Writeclean, maintainable, and well-documented code Optimizeapplications for maximum speed and scalability Writeunit and e2e tests Strongproficiency in React including hooks, context, and component lifecycle AdvancedTypeScript skills with strong typing and interface design Solidunderstanding of HTML5, CSS3, and modern JavaScript (ES6+) Knowledgeof state management patterns and libraries Understandingof RESTful APIs and asynchronous programming Experience with Git Who you are Experience with Vite for buildtooling and development workflow Knowledgeof TanStack libraries (React Query, React Table, React Router, etc.) Experiencewith testing frameworks (Jest, React Testing Library, Cypress) Familiarity with CI/CD pipelinesand deployment processes Frontend: React, TypeScript, Vite StateManagement: TanStack Query for server state management Styling:CSS Modules, Styled Components, or similar Testing:Jest, React Testing Library VersionControl: Git Build Tools: Vite for fastdevelopment and optimized builds 4 to 7+ years of experience Hands on experience in board designusing AM62x Sitara Processors, microprocessor TI, ARM cortex, or any one highspeed Processor from TI. Experience in interfacing of display,memory and communication modules with the processor. Experience on high speed and low speed interfaces like DDR ,memory, audio, USB,Ethernet, SATA, MIPI,HDMI, I2C SPI,UART, etc. Hands on experience in HardwareDevelopment Life Cycle like design, bringup, basic programming, testing andvalidation of boards, functional testing, trouble shooting, debugging andFailure analysis. Collaborating with cross function team in managing PCB layout, SI-PIsimulations, Software development, mechanical, thermal and other stakeholdersto ensure a cohesive and efficient system design. Should have knowledge on basics on programming and basic Linux commands Should be able to design the schematics in Altium and orcad. Hand on experience in using instrumentslike high speed Oscilloscopes, DMM, electronic loads etc. Good Communicationand interpersonal skill Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. If you receive any such communication, we stronglyadvise you to refrain from making any payments and to promptly report the incidentto us at hr@tessolve.com. Tessolve is not responsible for any losses incurreddue to such fraudulent activities