Timing Signoff Technical Lead

Intel

5 - 8 years

16 - 20 Lacs

bengaluru

Posted:1 week ago| Platform:

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Skills Required

technical lead rest medical apr eda static timing analysis soc ai asic design cloud formal verification internet of things computer architecture linux product development perl vlsi eda tools unix architecture communication skills

Work Mode

Work from Office

Job Type

Full Time

Job Description

In this position, the candidate will be part of a team implementing Integrated/Discrete Graphics blocks and AI SoCs on leading edge process technologies and EDA tools. The team is responsible for all SoC level physical design and optimization flows ranging from Floorplanning, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN aspects, Layout Verification, etc.
The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle.
Good interpersonal/communication skills are necessary due to the nature of work, size/complexity of products and the size of the team.The ideal candidate will have the skills and experience to lead SoC level timing convergence through a product development cycle.
The candidate must independently drive efforts to meet design/frequency requirements across hierarchies while utilizing knowledge of architecture, floorplan, data flow and process parameters.
Additionally, the candidate may need to work with stakeholders to set quality/timing limits based on both design commits and process knowledge.Qualifications:
Bachelor''s in Electrical/Computer Engineering with 13+ years relevant work experience, or Master''s in Electrical/Computer Engineering with 8+ years relevant work experience
Relevant coursework/experience should include: Logic Design/VLSI/ASIC Design/Computer ArchitectureGeneral knowledge of common ASIC style design flows - floorplanning, synthesis, place/route, layout verification, static timing analysis, formal/ layout verification
General knowledge of SoC hierarchical design and integration with experience in floorplan/timing integration of a variety of APR sub-blocksKnowledge and experience with Unix/ Linux, Perl and TCL in order to implement useable, flexible cshell/ perl/ tcl programs that automate tool/flow methodologiesHands-on experience with industry standard tools in VLSI/ASIC design

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