Job
Description
We are seeking highly motivated Test engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, delivery of DFT patterns and testing the patterns for IBM’s microprocessor chip design team. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4–9 years of experienceinATE test development, silicon debug, and production support for complex SoC or ASIC devices.
Strong expertise intest program development,test vector translation,timing setup, andATE bring-upworkflows.
Proven ability indebugging test failures, analyzing yield and parametric issues, and resolving silicon bring-up and characterization challenges.
Experience withRMA debug– reproducing, analyzing, and isolating failures in customer-returned or field-returned silicon.
Hands-on experience withPVT (Process, Voltage, Temperature) characterization, using ATE.
Experience inpattern generation,pattern retargeting, andvector-level debugusing standard ATE tools (e.g., Teradyne, Advantest).
Strong knowledge ofpin margin analysis,voltage/timing margining, and correlation between simulation and ATE results.
Proficient inautomation and scriptingusingVB (Visual Basic), Perl, Python, andTCLfor test flow automation, log parsing, and pattern manipulation.
Effective collaboration withcross-functional teamsincluding design, validation, product engineering, and silicon debug to ensure test robustness and quality.
Excellentdebug and bring-up skills– consideredkey requirementsfor this role.
Detail-oriented with solidanalytical and problem-solvingabilities.
Strong communication skills and ability to work acrossglobal teams.
Preferred technical and professional experience Experience withTeradyne UltraFlex (UFlex)tester is aplus.Familiarity withmicrocontroller architecture,embedded firmware, andfunctional verificationconcepts.
Experience inpost-silicon validation,system-level debug, andyield optimizationworkflows.
Knowledge ofprocessor-based test flows, scan diagnostics, and test time optimization