Sr. Physical Design Engineer

As a Sr. Physical Design Engineer at Lattice Semiconductor in Pune, India, you will have the opportunity to contribute to the HW design team focused on IP design and full chip integration. You will play a key role in implementing RTL to GDSII flow for complex designs and working on various aspects of physical design, including place & route, CTS, routing, floor planning, and power planning. Your experience in physical design signoff checks, scripting knowledge, and collaboration with cross-functional teams will be essential for success in this role. **Role Specifics:** - This is a full-time individual contributor position located in Pune, India. - Implement RTL to GDSII flow for complex designs. - Work on various aspects of physical design such as place & route, CTS, routing, floor planning, and power planning. - Conduct physical design signoff checks including timing closure, EM/RV, and physical verification. - Utilize scripting knowledge to improve design efficiency and methodology development. - Collaborate with RTL, DFT, verification, and full chip teams to ensure robust design implementation. - Share best-known-methods with the existing FPGA team and learn from the team about the complexities of highly programmable FPGA fabrics. **Accountabilities:** - Serve as a key contributor to FPGA design efforts. - Drive physical design closure of key ASIC blocks & full chip to achieve best power, performance, and area. - Ensure design quality through all physical design quality checks and signoff. - Develop strong relationships with worldwide teams. - Mentor and develop strong partners and colleagues. - Occasional travel may be required. **Required Skills:** - BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent. - 4+ years of experience in driving physical design activities of ASIC blocks and full chip. - Proficiency in industry standard physical design tools such as Innovus, Genus, Tempus, voltus, calibre, conformal, etc. - Independent worker with demonstrated problem-solving abilities. - Ability to work effectively with multiple groups across different sites and time zones. As a Sr. Physical Design Engineer at Lattice Semiconductor in Pune, India, you will have the opportunity to contribute to the HW design team focused on IP design and full chip integration. You will play a key role in implementing RTL to GDSII flow for complex designs and working on various aspects of physical design, including place & route, CTS, routing, floor planning, and power planning. Your experience in physical design signoff checks, scripting knowledge, and collaboration with cross-functional teams will be essential for success in this role. **Role Specifics:** - This is a full-time individual contributor position located in Pune, India. - Implement RTL to GDSII flow for complex designs. - Work on various aspects of physical design such as place & route, CTS, routing, floor planning, and power planning. - Conduct physical design signoff checks including timing closure, EM/RV, and physical verification. - Utilize scripting knowledge to improve design efficiency and methodology development. - Collaborate with RTL, DFT, verification, and full chip teams to ensure robust design implementation. - Share best-known-methods with the existing FPGA team and learn from the team about the complexities of highly programmable FPGA fabrics. **Accountabilities:** - Serve as a key contributor to FPGA design efforts. - Drive physical design closure of key ASIC blocks & full chip to achieve best power, performance, and area. - Ensure design quality through all physical design quality checks and signoff. - Develop strong relationships with worldwide teams. - Mentor and develop strong partners and colleagues. - Occasional travel may be required. **Required Skills:** - BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent. - 4+ years of experience in driving physical design activities of ASIC blocks and full chip. - Proficiency in industry standard physical design tools such as Innovus, Genus, Tempus, voltus, calibre, conformal, etc. - Independent worker with demonstrated problem-solving abilities. - Ability to work effectively with multiple groups across different sites and time zones.