38 Power Planning Jobs

You are a Physical Design Engineer who will be responsible for delivering high-performance design flows for high-performance SoCs in sub-10nm process for the mobile space. Your role will involve the following key responsibilities: - Hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post-route optimization, ECO implementation, and DRC closure. - Well-versed with high-frequency design & advanced tech node implementation. - In-depth understanding of PG-Grid optimization, including the identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience. - In-depth ...

Role : Sr Physical Design Lead/BE Integration This position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at Top level Key Responsibilities: Expertise in hierarchical RTL2GDSII design implementation Expertise in pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps Full chip Hierarchical Floor Planning, Block planning , block level constraints, hierarc...

#Urgent_Opening_for_Canvendor #Hiring: PD Floor Plan Engineer (5+ years) | Noida| Immediate Joiners Preferred Location: Noida, India Experience: 5+ years Notice period: Immediate #Key_Requirements: Own and drive floorplanning for complex SoC or IP blocks from RTL to GDSII. Collaborate with RTL, DFT, and architecture teams to understand design requirements and translate them into optimal floorplans. Perform macro placement , power grid planning , pin placement , and block-level partitioning . Analyze and optimize for congestion , timing , area , and power . Work closely with place & route , clock tree synthesis , and timing closure teams to ensure floorplan quality. Required Skills: Strong ha...

As a Digital Physical Design Engineer, you will play a crucial role in the physical implementation of complex digital integrated circuits. Your responsibilities will include: - Execute physical design activities such as floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). - Perform physical verification (DRC, LVS, Antenna) and address related issues efficiently. - Conduct power integrity analysis focusing on IR drop and EM, and optimize designs for enhanced power efficiency. - Participate in design-for-test (DFT) implementation and ensure the verification of test structures. - Collaborate closely with design, verification, and DFT teams to e...

As a candidate for the role at Ceremorphic AI, you will be responsible for owning and driving the physical implementation of next-generation SOCs. Your role includes the following key responsibilities: - Understand the requirements and define physical implementation methodologies. - Collaborate with architecture, design, front end, and CAD teams to deliver high-quality physical designs. - Implement and verify designs at all levels of hierarchy in the SOC. - Interact with foundry over matters of technology, schedule, and signoff. - Supervise resource allocation and scheduling. In order to excel in this position, you should possess the following key requirements: - Hands-on expertise in Floorp...

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Hands-on experience of different PnR steps including Floorplanning, Power planning, Placement...

As part of the DCS group at Microchip Technology, Inc., you will be involved in working on PCIe, CXL based Switches, Re-timers, and flash controllers for data-centers. **Responsibilities:** - Create Micro-Architecture Specification. - Collaborate with team members to design RTL and offer assistance in verification. - Focus on constraint development for CDC, RDC, and synthesis. - Review Test plans provided by the Verification team. - Assist the Emulation and Firmware team during bringup. **Requirements/Qualifications:** - Minimum B.Tech/M.Tech in Electronics or related field. - 10+ years of experience in RTL Design with leadership capabilities. **Key Skills:** - Proficient in VLSI logic desig...

Job Description: As an ASIC Physical Design Engineer, you will need to have 5 years of physical design experience, with recent successful tapeouts in deep submicron technologies (45nm and below). Your role will involve a strong knowledge of Full chip floor planning, partitioning, and Detailed PD Flow. You should also have a proven ability to handle a team with respect to Block to full chip floor plan. Your responsibilities will include Block level and Full Chip Floor planning, Metal Layer estimation-planning, power planning, and Full Chip Signoff closure. Qualifications Required: - Minimum of 5 years of physical design experience - Recent successful tapeouts in deep submicron technologies (4...

Role Overview: You will be stepping into a deep technical leadership position where your main focus will be on architecting and guiding turnkey SoC physical design projects. Your role will involve extensive hands-on expertise in RTL2GDS implementation at advanced nodes like 3nm/5nm, customer interaction, and taking ownership of project methodology, technical quality, and solution engineering from start to finish. Key Responsibilities: - Define and drive end-to-end RTL-to-GDSII flows customized for specific customer technology, tools, and deliverables. - Lead complex top-level and hierarchical SoC designs to ensure quality and compliance with signoff requirements. - Provide guidance on floorp...

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What You'll Do End-to-End ASIC Implementation Lead...

As a Sr. Physical Design Engineer at Lattice Semiconductor in Pune, India, you will have the opportunity to contribute to the HW design team focused on IP design and full chip integration. You will play a key role in implementing RTL to GDSII flow for complex designs and working on various aspects of physical design, including place & route, CTS, routing, floor planning, and power planning. Your experience in physical design signoff checks, scripting knowledge, and collaboration with cross-functional teams will be essential for success in this role. **Role Specifics:** - This is a full-time individual contributor position located in Pune, India. - Implement RTL to GDSII flow for complex desi...

Position: Sr Design Lead (PNR)/STA Experience: 8-12 years relevant experience. Location Bangalore/Hyderabad Tessolve Semiconductors a venture of Hero Electronix , part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2300+ employees worldwide. We are Global Multi- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even ...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to ...

Job Designation: ASIC Physical Design Engineer Brief Role Should have 5 years of physical design experience, with recent successful tapeouts in deep submicron technologies (45nm and below). Strong knowledge of Full chip floor planning, partitioning, and Detailed PD Flow. Proven ability to handle a team with respect to Block to full chip floor plan. Block level and Full Chip Floor planning, Metal Layer estimation-planning, power planning, Full Chip Signoff closure. Industry: Semiconductor Location: Bangalore

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be part of a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. **Key Responsibilities:** - Plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, and packaging. - Bring-up yield and test systems, FPGA, and/or DSP systems for cutting-edge product launches. - Collaborate with cross-functional teams to develop solutions and meet performance requirements. - Hands-on experience of different PnR steps including ...

You will be working as a Qualcomm Hardware Engineer at Qualcomm India Private Limited, a leading technology innovator that drives digital transformation to create a smarter, connected future for all. In this role, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements. Key Responsibilities: - Demonstrating 8+ years of hands-on experience in different PnR steps such as Floorplanning, Power planning, Placement & Optimization, CTS, Routing, ...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop innovative solutions and meet performance requirements. Key Responsibilities: - Hands-on experience in different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. - Proficiency in high frequency design & advanced tech node implement...

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location: Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge: ICC, innovus, primetim...

As an experienced Physical Design Engineer, you will be responsible for executing block level P&R and Timing closure activities. Your primary role will involve owning up block level P&R and performing Netlist2GDS on blocks. You will be working on the implementation of multimillion gate SoC designs in cutting-edge process technologies such as 28nm, 16nm, 14nm, and below. Your expertise should cover various aspects of physical design, including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal I...

As a Physical Design Engineer at our company, you will be part of a dynamic team responsible for delivering high-performance design flows for advanced SoCs in sub-10nm process technology for the mobile space. Your role will involve hands-on experience in various PnR steps such as Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. Additionally, you will be expected to: - Demonstrate expertise in high-frequency design and advanced tech node implementation - Utilize in-depth understanding of PG-Grid optimization for identifying high vs low current density paths, layer/via optimization, and...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity ...

As the candidate for the position at Ceremorphic AI hardware, you will be responsible for owning and driving the physical implementation of next-generation SOCs. Your role will involve understanding requirements and defining physical implementation methodologies. You will collaborate with architecture, design, front end, and CAD teams to ensure the delivery of high-quality physical designs. Additionally, you will be responsible for implementing and verifying designs at all levels of hierarchy in the SOC. Your role will also entail interacting with the foundry on matters related to technology, schedule, and signoff, as well as supervising resource allocation and scheduling. Key Responsibiliti...

As a member of our team at Google, you will have the opportunity to work on developing custom silicon solutions that drive the future of Google's direct-to-consumer products. You will be at the forefront of innovation, contributing to the enhancement of Power Performance Area (PPA) through the utilization of machine learning techniques. Your expertise in physical design and machine learning will be pivotal in shaping the next era of hardware experiences, ensuring unparalleled performance, efficiency, and integration. **Key Responsibilities:** - Contributing to the enhancement of Power Performance Area (PPA) through the utilization of machine learning techniques. - Tackling technical challeng...

Role Overview: You will be working as a deep technical leadership role focused on architecting and guiding turnkey SoC physical design projects. Your main responsibility will be to have extensive hands-on expertise in RTL2GDS implementation at advanced nodes (3nm/5nm), interface with customers, and ensure project methodology, technical quality, and solution engineering end to end. Key Responsibilities: - Define and drive end-to-end RTL-to-GDSII flows, tailored for customer-specific technology, tools, and deliverables. - Lead complex top-level and hierarchical SoC designs, ensuring quality and signoff compliance. - Guide floorplan strategy, power planning, PPA closure, IR/EM signoff, and inte...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - 8-10 years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure - ...