13 Power Planning Jobs

As a CPU Physical Design Lead at 7Rays Semiconductors, you will be responsible for the development of high-speed cores such as CPU, GPU, and DDR. With over 10 years of experience, you must possess significant knowledge in synthesis, constraints, and physical design, keeping power, performance, and area (PPA) in mind throughout the process. Collaboration with RTL designers for optimizations and feedback will be a key part of your role, ensuring efficient floorplanning for multi-core, L2 & L3, and power planning up to Bumps. Your expertise in silicon margins, VT trade-off, power, and area impact will be vital in making informed decisions. Understanding critical paths, pipelining, latency, and implementing super buffers will be within your scope, contributing to the overall efficiency and performance of the designs. Additionally, having knowledge in low power implementation will be considered an advantage in this position. At 7Rays Semiconductors, we specialize in providing custom SoC design solutions to top semiconductor and system companies. Working closely with our clients, we aim to build effective partnerships and deliver high-quality solutions tailored to their specific needs. With a dedicated engineering team and a successful track record in project executions, we are committed to excellence and innovation in SoC design, development, and deployment to support our customers" product goals.,

The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST, and ATPG, strong background in TCL/Perl programming, and expertise in double patterning process nodes are required. Preferably, expertise in Cadence RTL-to-GDSII flow is also desired.,

Qualcomm India Private Limited is looking for a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, DSP systems, equipment and packaging, and test systems. The aim is to develop cutting-edge, world-class products and collaborate with cross-functional teams to meet performance requirements. Qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience in the relevant field will also be considered. The key responsibilities of this role involve IR Signoff CPU/high-performance cores, Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs, development of PG Grid spec for different HM, validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks, validating the IR Drops using Static IR, Dynamic IR Vless & VCD Checks, working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations, and possessing good knowledge of PD. Proficiency in scripting languages such as Python, Perl, and TCL is required. It is essential to have hands-on experience in PDN Signoff using Redhawk/RHSC/Voltus at block level/SOC Level, a good understanding of Power Integrity Signoff Checks, familiarity with Innovus for RDL/Bump Planning/PG eco, and the ability to communicate effectively with multiple global cross-functional teams. Experience with tools like Redhawk, Redhawk_SC, Innovus/Fusion Compiler, Power Planning/Floor planning, and Physical Verification is an added advantage. Knowledge of LSF/compute optimization is also beneficial. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible in order to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience is also acceptable. The ideal candidate will have 5 to 8 years of hands-on experience in different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. Furthermore, expertise in high frequency design, advanced tech node implementations, PG-Grid optimization, custom clock tree design, placement density/congestion management, and PnR tool optimization is required. Proficiency in automation using Perl/Python and tcl, as well as excellent communication skills and the ability to work effectively in a cross-functional team environment, are also essential. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations are available for applicants who require assistance during the application/hiring process. It is expected that all employees at Qualcomm adhere to company policies and procedures, including those related to security and confidentiality. Staffing and recruiting agencies are advised that the Qualcomm Careers Site is intended for individuals seeking direct employment opportunities with Qualcomm and unsolicited submissions will not be considered. For further information about this role, please reach out to Qualcomm Careers for assistance.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Hardware Engineer at Qualcomm, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to ensure solutions meet performance requirements. To be considered for this role, you must have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience will also be considered. The ideal candidate will have at least 8 years of hands-on experience in various PnR steps, high frequency design, advanced tech node implementations, PG-Grid optimization, and custom clock tree design. Proficiency in automation using Perl/Python and tcl is preferred, along with strong communication skills and the ability to work effectively in a cross-functional team environment. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities throughout the application and hiring process. If you require accommodation, you can reach out to disability-accommodations@qualcomm.com. Please note that this email address is solely for disability accommodation requests and not for application updates or resume inquiries. As a Hardware Engineer at Qualcomm, you will be expected to adhere to all relevant policies and procedures, including those related to security and protection of confidential information. Staffing and recruiting agencies are advised that Qualcomm's Careers Site is intended for individual job seekers only, and unsolicited submissions will not be accepted. For more information about this exciting opportunity, please contact Qualcomm Careers.,

We are seeking enthusiastic individuals to join our team at Alphawave Semi, where we enable the next generation of digital technology by accelerating critical data communication. As a Physical Design Engineer in our IP Scaling (IPS) organization, you will play a key role in creating customized IP for our expanding customer base, delivering high-speed interconnect solutions for various industries such as High Performance Computing and Artificial Intelligence. Your responsibilities will include driving the backend process through the entire implementation flow, with a focus on floor-planning, power planning, low-power design, place & route optimization, clock tree synthesis, static timing verification, and physical verification. We are looking for someone with at least 5 years of Physical Design experience, a Bachelor's degree in Electrical or Computer Engineering (or equivalent), and advanced technology node experience. Attention to detail, strong collaboration and communication skills, analytical problem-solving abilities, consistency, and self-motivation are essential qualities we seek in our team members. At Alphawave Semi, we offer a flexible work environment that supports personal and professional growth. In addition, we provide a competitive compensation package, Restricted Stock Units (RSUs), opportunities for advanced education from premium institutes, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. We are committed to promoting diversity and inclusivity, welcoming applicants of all backgrounds and providing accommodations during the recruitment process. If you are passionate about driving innovation in the world of data communication and are eager to work with a dynamic team of talented individuals, we encourage you to apply for the Physical Design Engineer position at Alphawave Semi.,

Foundry Services (FS) is an independent foundry business established to meet customers" unique product needs. With the first Open System Foundry model globally, combined offerings include wafer fabrication, advanced process, packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities. This helps customers build innovative silicon designs and deliver customizable products from Intel's secure, resilient, and sustainable supply source. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group, responsible for bringing the best of Intel technologies to FS customers, accelerating solutions from architecture to post-silicon validation. We are seeking an experienced Floorplan Engineer to focus on floor plan, die estimation, and power planning for high-performance designs. Responsibilities include establishing integration plans for die with optimization for package and board constraints, bump planning, die file generation, collaborating with architects for IP or SoC placement optimization, clocking and dataflow collaboration, deriving specifications for IP blocks, coordinating with power delivery team, maximizing die-per-reticle/good-die-per-wafer, RDL routing knowledge, and package integration before tape-out. **Qualifications:** - 12+ years of experience after a Bachelor or Master of Engineering degree in Electrical/Electronic/VLSI Engineering or related field. - Led multiple SOCs as SOC Floorplan lead, expertise in design planning, die estimation, knowledge of clocking, high-speed design signal routing, industry protocols, IP architecture, library/memory/technology/submicron issues. - Strong teamwork, flexibility, ability to thrive in a dynamic environment. **Job Type:** Experienced Hire **Shift:** Shift 1 (India) **Primary Location:** India, Bangalore Intel Foundry is committed to transforming the global semiconductor industry by providing cutting-edge silicon process and packaging technology. Innovating under Moore's Law, fostering collaboration, and investing in geographically diverse manufacturing capacities. Intel Foundry enables the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, dedicated to customer success with full P&L responsibilities.,

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understanding of the Physical Verification flow, with experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues primarily using the Calibre tool. Additionally, a deep understanding of ESD, latch-up, etc., is required. You will be responsible for owning and executing Physical Verification activities at the Top/Block level. Collaborating closely with the PD team to address their PV issues and suggest solutions is a key aspect of the role. Working with CAD team to refine existing flows/methodologies and resolve issues is also part of the job scope. Experience in IO, Bump planning, RDL routing Strategy, and developing/implementing timing and logic ECOs are considered advantageous. Knowledge of tools like Innovus/FC for DRC fixing, Python, PERL/TCL scripting, and the ability to plan, work independently, and coordinate with cross-functional teams are essential. Closing sign off DRC based on PNR markers is a plus. The ideal candidate should have experience with physical verification checks such as DRC, LVS, Antenna, ERC, PERC, ESD, etc. Experience with PnR tools like ICC/Innovus and understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV is required. A good overall understanding of the Custom IC design flow, layouts, and backend tool flow would be beneficial. Hands-on experience with tools like Innovus/Fusion Compiler, Tech lef is preferable. People management, floorplanning, power planning, and PDN experience are considered a big plus. The ability to script in TCL/PERL and familiarity with physical convergence in PnR tools are also advantageous. In return, we offer a competitive salary, performance-based bonuses, comprehensive benefits package including health insurance, retirement plans, and paid time off. Additionally, you will have opportunities for professional development and career growth in a collaborative and innovative work environment with state-of-the-art facilities.,

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field. We are seeking PDN engineers with EMIR and PG planning expertise and a minimum of 4 years of experience. Responsibilities include IR signoff for CPU/high-performance cores, Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP, Development of PG Grid spec for different HM, and validating PG Grid and IR Drops. Additionally, working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations is crucial to enhance PDN Design. The desired skill set includes hands-on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level, proficiency in scripting languages like Tcl and Perl, and familiarity with tools such as Redhawk, Redhawk_SC, Innovus, and Fusion Compiler. The ability to communicate effectively with global cross-functional teams and experience in Power Planning/Floorplanning and Physical Verification is an added advantage. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. Abiding by all applicable policies and procedures, including security requirements, is expected from Qualcomm employees. Please note that our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. Unsolicited submissions will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group, specifically focusing on Hardware Engineering. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams to meet performance requirements is a key aspect of this role. Key responsibilities for this position include: - IR Signoff CPU/high performance cores - Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs - Development of PG Grid spec for different HM - Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks - Validating the IR Drops using Static IR, Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops - Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design - Good knowledge on PD would is desirable - Proficiency in Python, Perl, TCL The ideal candidate should possess the following qualifications and skills: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field - 4+ years of experience in PDN engineering with EMIR and PG planning expertise - Hands-on experience in PDN Signoff using Redhawk/RHSC/Voltus at block level/SOC Level - Good understanding of Power Integrity Signoff Checks - Proficiency in scripting languages (Tcl and Perl) - Familiarity with Innovus for RDL/Bump Planning/PG eco - Ability to effectively communicate with global cross-functional teams - Experience with tools such as Redhawk, Redhawk_SC, Innovus/Fusion Compiler, Power Planning/Floorplanning, and Physical Verification Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. It is essential for Qualcomm employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised not to use Qualcomm's Careers Site for submissions, as unsolicited applications will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

You are a Physical Design Engineer with 2-5 years of hands-on experience in different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. You should be well versed with high frequency design & advanced tech node implementation, in-depth understanding of PG-Grid optimization, custom clock tree design, and tackling high placement density/congestion bottlenecks. Your expertise should include identifying high vs low current density paths, layer/via optimization, and Adaptive PDN experience. You must have knowledge of custom clock tree designs such as H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Familiarity with PnR tool knobs/recipes for PPA optimization is essential. Experience in automation using Perl/Python and tcl is required. Good communication skills are necessary as you will be working in a cross-site cross-functional team environment. The ideal candidate will have a BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or an equivalent field with a minimum of 3 years of relevant experience. This is a great opportunity to be part of a fast-paced team responsible for delivering high-performance designs for high performance SoCs in sub-10nm process for the mobile space.,

As a Principal Physical Design Engineer focusing on New Product Development in Power Management at OnSemi in Bengaluru, India, you will play a crucial role in the development of Power management products for various applications such as consumer, industrial, and automotive sectors. Your responsibilities will include leading the P&R process, power planning, floor planning, clock tree building, congestion analysis for complex multi-power domain designs, and continuously seeking improvements in existing flows and methods to enhance Performance, Power, and Area (PPA) metrics. Your role will require strong problem-solving skills with a deep understanding of technical issues, allowing you to collaborate effectively with both analog and digital technical staff members. You should possess a comprehensive understanding of the end-to-end digital design flow and have hands-on experience in IR & power analysis tools and flows. Proficiency in Verilog, TCL, and Perl/Python programming languages is essential for this position. Onsemi, a company focused on driving disruptive innovations in automotive and industrial end-markets, aims to create intelligent power and sensing technologies to address complex global challenges. The company's innovative product portfolio contributes to building a safer, cleaner, and smarter world by leveraging megatrends like vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. To qualify for this role, you should hold a Bachelor's degree in Electrical Engineering or a related field with at least 8 years of experience, or a Master's degree with 7 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. Your expertise should cover RTL design, ASIC synthesis, timing analysis, CDC, P&R, and UPF methodologies. Additionally, a proven track record of releasing complex ICs to the market and excellent cross-functional communication skills are required to succeed in this position. At Onsemi, we are dedicated to attracting high-performance innovators and providing a positive recruitment experience for all candidates, reflecting our commitment to being a great place to work. If you are passionate about driving innovation in Power Management and contributing to a better future, we encourage you to join our dynamic team and be part of our journey towards creating a more sustainable and intelligent world.,